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Clock balancing is even distribution of load on the different clock paths so that skew will be minimum in the design. There are several techniques through which you can balance the skew such as
1. Gate/Buffer Sizing--sizes up/down buffers/gates to improve both skew and insertion delay( In this method the clock tree structure will not be modified)
2. Gate/Buffer relocation--The position of buffer will be adjusted so that skew/insertion delay is reduced. The hierarchy of the clock tree will remain intact in this method.
3.delay insertion--Delay is inserted for shortest paths(Not advisable because this can lead to other timing violations)
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