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Re: class AB output stage
This is the best way:
"Compact Low-Voltage Power-Efficient Operational Amplifier Cells for VLSI", by Klaas-Jan de Langen and Johann H. Huijsing, IEEE Journal of Solid-State Circuits, vol. 33, No. 10, Oct. 1998
A native nmos is made by depositing the gate oxide directly on the lightly-doped substrate. A normal nmos is made by an p-implant into p-substrate so that a higher-doped area below the gate is formed (so-called p-well) which increases the threshold voltage. When isolated nmos is made, a deep...
adc using r-2r
It's very hard to acheve 12 bit accuracy matching with R2R. You will have to use thermometer coded ladder for MSBs, but even with that the area has to be very large in order to achieve the required matching. Also pay attention to resistors nonlinearity, your resistors may not be...
No, that's a wrong place to break the loop because it will delete the nondominant pole formed by the output impedance of EA and gate cap of the pass MOSFET.
Are you sure you need chopping? Ususally for regular BGR this is not necessary unless you need very low noise or very high accuracy. Just use large input MOSFETS to minimize offset and 1/f noise.
No. If you want less than 2mV overall accuracy over temperature and corners then the olny way to compensate for process variations is trimming. You can trim the resistor which is in series with BJT/diode.
Bandgaps have two feedback loops - one negative and the oher one positive, so they are prone to instability. You have to break the loop AC-wise at the output of the opamp before it splits into two loops and measure the phase margin there. Usually there is no need for special compensation...
cmos lateral pnp
OK, I'll try, but I can't see lateral PNP in their standard models and libraries even for RF/mixed signal process, they only have vertical PNPs and NPNs there.
cmos pnp
Has anyone used or have any papers/info on a lateral PNP in TSMC 0.18 or 0.25u? Optimum layout, models? What is the realistcly achievable beta?
A word of caution: to design low noise chopper-stabilized amp, which is going to be switched cap kind of circiuit, you will need fairly high caps to keep the kT/C noise low. This might be difficult to achieve on chip, although it's not a problem if you have an option of using off-chip caps...
trim bandgap
Dear collegues, has anybody designed bandgaps in CMOS for mass-production chips? Please share you experience.
- How did you implement the trimmimg, what is the best way to trim?
- How to trim a bandgap in production testing if the chip is tested only at room temperature? And what...
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