Need help on the design of a LDO

[xihuwang]

ldo vref 1085

Hi, everyone
The below figure is a LDO. The upper part is the structure and lower part is
the test circuits for the frequency response of loop gain.
The frequency compensation method , in my opinion, is Miller compensaiton with
current buffer to block forward feedback.
R1, C1 : the output parameter at the output of the errAmp
R2,C2 : the output parameter at the output of the buffer
Cm : Miller cap
My questions are :
1. What is the analytic equation of the loop gain ?
2. And what are the poles and zeros position or anlytic eqution of them?
3. I use a big inductance and cap to break the loop to calculate the loop gain
equation. Is the scheme right (lower part of the figure) ?


Added after 22 minutes:

 

[xihuwang]

Any one can help me ?

 

[LvW]

I can give you a recommendation regarding simulation of the loop gain.
You should not use the crude method with large L and large C for breaking the loop and feeding in the testsignal.
It is better to break the loop at the ouput of the opamp (low output resistance) and to place the ac source in line between opamp output (out) and the feedback path (in).
Then the loop gain is simply V(out)/V(in).

Added after 1 hours 13 minutes:

I don´t quite understand your circuitry: Where is the path beween LDO output and the Vo input of the error amplifier ?

 

[quaternion]

What appears from the second picture is that you feed back the output voltage directly to the error amplifier input !! this means that u are using Vref = Vout !

Also u are using the EA input transistor as the compensation buffer!!

well if these are right why you are cutting the loop in the compensation path not in the feedback path??

 

[DenisMark]

You break the loop in wrong place.
You have to break between output and input of EA on right side of picture.

 

[evi]

I can give you a recommendation regarding simulation of the loop gain.
You should not use the crude method with large L and large C for breaking the loop and feeding in the testsignal.
It is better to break the loop at the ouput of the opamp (low output resistance) and to place the ac source in line between opamp output (out) and the feedback path (in).

No, that's a wrong place to break the loop because it will delete the nondominant pole formed by the output impedance of EA and gate cap of the pass MOSFET.

 

[LvW]

No, that's a wrong place to break the loop because it will delete the nondominant pole formed by the output impedance of EA and gate cap of the pass MOSFET.

Yes, in principle you are right - if this pole is really of interest. But as you have mentioned, it is a "nondominant pole" - and there will be only minor influence on the loop gain.
Therefore, it is not "the wrong place" - it is a very proven method for output impedances which are so low that their influence can be neglected.
If also nondominant poles are to be considered a more complicated method has to be applied (as proposed by Middlebrook).