evi
Junior Member level 3
trim bandgap
Dear collegues, has anybody designed bandgaps in CMOS for mass-production chips? Please share you experience.
- How did you implement the trimmimg, what is the best way to trim?
- How to trim a bandgap in production testing if the chip is tested only at room temperature? And what is the point of trimming if the actual temerature sweep test (which is necessary to accurately determine the trimming) is not possible in production anyway.
- What realistic accuracy and temperature stability can be achieved in mass production?
- Did you find that the actual voltage of the optimum point (temperature curve peak when positioned at 25C) is different from theoretical 1.24V and also is different from the value that simulation gives? I designed a trimmable bandgap in TSMC 0.18u and found from lab testing that it's optimum point voltage is 1.18V, while simulations give me around 1.25V. 8O I'm confused. May be TSMC models for BJT are not accurate enough for bandgap simulation?
Dear collegues, has anybody designed bandgaps in CMOS for mass-production chips? Please share you experience.
- How did you implement the trimmimg, what is the best way to trim?
- How to trim a bandgap in production testing if the chip is tested only at room temperature? And what is the point of trimming if the actual temerature sweep test (which is necessary to accurately determine the trimming) is not possible in production anyway.
- What realistic accuracy and temperature stability can be achieved in mass production?
- Did you find that the actual voltage of the optimum point (temperature curve peak when positioned at 25C) is different from theoretical 1.24V and also is different from the value that simulation gives? I designed a trimmable bandgap in TSMC 0.18u and found from lab testing that it's optimum point voltage is 1.18V, while simulations give me around 1.25V. 8O I'm confused. May be TSMC models for BJT are not accurate enough for bandgap simulation?