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Recent content by etherios

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    Help in atmega16 and USART

    usart atmega16 Ok i am using a STK500 with an atmega16 and for debugging a JTAGICE mkII. I use assembly language. I have observed the following a. I cannot see the content of baud rate registers (UBRRH+UBRRL). It seems to be empty. b. I have to re-initialise the UBRR every time i have to write...
  2. E

    Capturing Switching Activity Synopsys-Modelsim

    prime power link db synopsys the problem is that power is also up to the spatial-temporal dependence of the inputs so in order to measure the exact power you need this kind of simulation. If anyone knows what can i do with the size of vcd file plz tell me
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    Capturing Switching Activity Synopsys-Modelsim

    modelsim vcd add power analysis Ok according to manual vcd add captures the changes to internal variables. All this fuss is because i want to import it to primepower
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    Capturing Switching Activity Synopsys-Modelsim

    activity file for modelsim ok i use the following flow and i like to ask your opinion i synthesize the adder.vhd using the following script set search_path /home/kanagno/projects/hardware/adder set link_library /usr/synopsys/umc_libraries/UMCL18U250D2_2.4/design_compiler/umcl18u250t2_typ.db...
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    Capturing Switching Activity Synopsys-Modelsim

    switching activity file format what do you mean with vital primitives?
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    Capturing Switching Activity Synopsys-Modelsim

    synopsys modelsim Ok Back again after so long. Happy new year to all of you. I want to capture the switching activity of a ripple adder I have the following files the adder.vhd which describes the adder library IEEE; use IEEE.std_logic_1164.all; entity adder is port ( a,b,c :in std_logic...
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    What is the best way to reduce power for low power ASIC?

    Re: LOW POWER ASIC generally the higher the level of abstraction the better ste savings in power
  8. E

    A question about PrimePower!

    I does not work also in 2003.12. But you can type report_wire * instead of -all and then to add your options
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    What is a glitch and how to if an equation has a glitch?

    Re: Glich Gliches or dynamic hazards are unwanted transitions which occur because gates have non zero propagation delays. Finding if an equation has glitches needs first to be synthesized, and then check if the paths to the output are balanced (have the same propagation delay) then glitches...
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    Looking for latest references about voice recognition

    Voice Recognition I am looking for information about this topic especilly of the last 4 years.
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    Synopsys synthesis of a full adder cell

    Re: Synopsys- Synthesis After so long i have found a solution at least for the structural description of the circuit. If anyone can provide something for the behavioral plz tell me. Here is the listing library IEEE; use IEEE.std_logic_1164.all; library GTECH; use gtech.gtech_components.all...
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    Synopsys synthesis of a full adder cell

    Re: Synopsys- Synthesis how can we do this in rtl description? Can you be more specific? If you can send me an example
  13. E

    Synopsys synthesis of a full adder cell

    I am describing a full adder cell in synopsys and i want to be synthesised with the full adder cell of my 0.13 library but the tool uses the gate implementation. What should i do in order to be synthesised with that cell i want from the library?
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    what the power vaule means in Libray Compiler ? uW/MHZ?

    I don't think that there is a reason for you to build a library with the short circuit dissipation of several digital circuits. If you the rise time and fall time of the gates are equal then the short circuit dissipation is minimized. I can cite you to a paper if you need further informations.
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    what the power vaule means in Libray Compiler ? uW/MHZ?

    rise_constraint What do you mean with internal power? Leakage or short circuit?
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