etherios
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synopsys modelsim
Ok Back again after so long. Happy new year to all of you.
I want to capture the switching activity of a ripple adder
I have the following files
the adder.vhd which describes the adder
library IEEE;
use IEEE.std_logic_1164.all;
entity adder is
port (
a,b,c :in std_logic;
sum,carryut std_logic);
end adder;
architecture adder of adder is
begin
sum <= a xor b xor c;
carry <= (a and b) or (b and c) or (c and a);
end adder;
and the adder_n.vhd which describes the rippler adder
library IEEE;
use IEEE.std_logic_1164.all;
entity adder_n is
generic (N: integer :=8);
port(
a,b:in std_logic_vector(0 to N-1);
cin:in std_logic;
sut std_logic_vector(0 to N-1);
coutut std_logic);
end adder_n;
architecture struct of adder_n is
component adder
port (
a,b,c: in std_logic;
sum,carryut std_logic);
end component;
signal c: std_logic_vector(0 to N);
begin
c(0)<= cin;
cout<= c(N);
adders: for k in 0 to N-1 generate
A1:adder port map(a(k),b(k),c(k),s(k),c(k+1));
end generate adders;
end struct;
i use the following script in synopsys
set search_path /home/kanagno/projects/hardware/adder
set link_library /usr/synopsys/umc_libraries/UMCL18U250D2_2.4/design_compiler/umcl18u250t2_typ.db
set target_library /usr/synopsys/umc_libraries/UMCL18U250D2_2.4/design_compiler/umcl18u250t2_typ.db
set symbol_library /usr/synopsys/umc_libraries/UMCL18U250D2_2.4/design_compiler/umcl18u250t2.sdb
analyze -format vhdl adder.vhd
elaborate adder
analyze -format vhdl adder_n.vhd
elaborate adder_n
link
uniquify
compile
write -format vhdl -output synthesized.vhd
now how can i use the synthesized.vhd in modelsim in order to capture the switching activity of the design using a testbench file?
Ok Back again after so long. Happy new year to all of you.
I want to capture the switching activity of a ripple adder
I have the following files
the adder.vhd which describes the adder
library IEEE;
use IEEE.std_logic_1164.all;
entity adder is
port (
a,b,c :in std_logic;
sum,carryut std_logic);
end adder;
architecture adder of adder is
begin
sum <= a xor b xor c;
carry <= (a and b) or (b and c) or (c and a);
end adder;
and the adder_n.vhd which describes the rippler adder
library IEEE;
use IEEE.std_logic_1164.all;
entity adder_n is
generic (N: integer :=8);
port(
a,b:in std_logic_vector(0 to N-1);
cin:in std_logic;
sut std_logic_vector(0 to N-1);
coutut std_logic);
end adder_n;
architecture struct of adder_n is
component adder
port (
a,b,c: in std_logic;
sum,carryut std_logic);
end component;
signal c: std_logic_vector(0 to N);
begin
c(0)<= cin;
cout<= c(N);
adders: for k in 0 to N-1 generate
A1:adder port map(a(k),b(k),c(k),s(k),c(k+1));
end generate adders;
end struct;
i use the following script in synopsys
set search_path /home/kanagno/projects/hardware/adder
set link_library /usr/synopsys/umc_libraries/UMCL18U250D2_2.4/design_compiler/umcl18u250t2_typ.db
set target_library /usr/synopsys/umc_libraries/UMCL18U250D2_2.4/design_compiler/umcl18u250t2_typ.db
set symbol_library /usr/synopsys/umc_libraries/UMCL18U250D2_2.4/design_compiler/umcl18u250t2.sdb
analyze -format vhdl adder.vhd
elaborate adder
analyze -format vhdl adder_n.vhd
elaborate adder_n
link
uniquify
compile
write -format vhdl -output synthesized.vhd
now how can i use the synthesized.vhd in modelsim in order to capture the switching activity of the design using a testbench file?