what the power vaule means in Libray Compiler ? uW/MHZ?

[hgz]

min_pulse_width_low

Hi,All:

what the power vaule means in Libray Compiler ? uW/MHZ or other ?

Best Regards!

 

[etherios]

what is setup_rising

The power dissipation (dynamic) is given by
Pdyn=C*Vdd^2*P*f the ratio Pdyn/f is the number you are asking.

 

[hgz]

setup_rising

thanks you.That means that if I the value is 0.1, it power is 10 unit if it is woking in 100MHZ, and the power is 20unit when it working in 200mhz?

Best Regards!

 

[etherios]

min_pulse_width_low clock

Exactly, usually libraries have an equation where you can caclulate the power dissipation of a digital circuit.

 

[hgz]

uw/mhz

Hi,
when I genearte RF2R2W power, I get I=5mA, worst case V=1.62v 200Mhz,so the power should be 5*1.62v=8.1mW, the value in the library should be 8.1/200=0.0405 mw/MHZ, I checked the compiled library it should should be 40.5, what the unit should be in compiled library ?

Best Regards!

 

[etherios]

internal_power unit

the power dissipation is connected also with the switching activity and the capacitance. Check your library there is an equation for power estimation. It is not that straightforward.

 

[hgz]

uw mhz

Hi,
Thant you , if I want to generate a library with power information,what should I do ?

Best Regards!

 

[hgz]

power uw/mhz

Hi,
The power I want to generate is internal_power.

Best Regards!

 

[etherios]

rise_constraint

What do you mean with internal power? Leakage or short circuit?

 

[hgz]

Hi,
It meas short_circuit power.
During switching, a circuit dissipates internal power by the charging
or discharging of any existing capacitances internal to the cell. The
definition of internal power includes power dissipated by a momentary
short circuit between the P and N transistors of a gate, called shortcircuit
power.


Best Regards!

 

[etherios]

I don't think that there is a reason for you to build a library with the short circuit dissipation of several digital circuits. If you the rise time and fall time of the gates are equal then the short circuit dissipation is minimized. I can cite you to a paper if you need further informations.

 

[hgz]

Hi,

Sorry,I am a little confuse of that. For a cell internal power may meas short circuit power,but for a circuit compose lots of cells, they are not the same definition. In my opition,it may meas dynamic power.
I have ftp some files ,include library and verilog code .It generate by memroy compiler. Please see the library file, the internal power problem is in there. thanks.


Best Regards!

 

[hgz]

Hi,
here they are.I can not ftp .lib file to you.If you want I will email to you later.
Here is the power description in libray file:
***************************************
pin(CLKB) {
direction : input;
capacitance : 0.070
clock : true;
min_pulse_width_low : 0.129;
min_pulse_width_high : 0.115;
min_period : 0.803;
max_transition : 2.100;
internal_power(){
when : "CENB";
rise_power(RF2SH_200_passive_energy_template_1x2) {
index_1 ("0.0 1.0");
values ("0.000, 0.000")
}
fall_power(RF2SH_200_passive_energy_template_1x2) {
index_1 ("0.0 1.0");
values ("0.0, 0.0")
}
}
internal_power(){
when : "!CENB";
rise_power(RF2SH_200_passive_energy_template_1x2) {
index_1 ("0.0 1.0");
values ("37.170, 37.170")
}
fall_power(RF2SH_200_passive_energy_template_1x2) {
index_1 ("0.0 1.0");
values ("0.0, 0.0")
}
}
timing() {
related_pin : "CLKA" ;
timing_type : setup_rising ;
rise_constraint(scalar) {
values ("0.413")
}
}
}
pin(CLKA) {
direction : input;
capacitance : 0.087
clock : true;
min_pulse_width_low : 0.158;
min_pulse_width_high : 0.127;
min_period : 1.114;
max_transition : 2.100;
internal_power(){
when : "CENA";
rise_power(RF2SH_200_passive_energy_template_1x2) {
index_1 ("0.0 1.0");
values ("0.000, 0.000")
}
fall_power(RF2SH_200_passive_energy_template_1x2) {
index_1 ("0.0 1.0");
values ("0.0, 0.0")
}
}
internal_power(){
when : "!CENA";
rise_power(RF2SH_200_passive_energy_template_1x2) {
index_1 ("0.0 1.0");
values ("62.377, 62.377")
}
fall_power(RF2SH_200_passive_energy_template_1x2) {
index_1 ("0.0 1.0");
values ("0.0, 0.0")
}
}
timing() {
related_pin : "CLKB" ;
timing_type : setup_rising ;
rise_constraint(scalar) {
values ("0.413")
}
} }

..........

 

[sandusty]

Power could be decomposed into three parts:

Static power (leakage)
Dynamic: Short circuit
Dynamic: Charging /discharging the load (wire and gate)

p = c* v^2 * f
covered the third part.

Most of the libraries did NOT include the leakage.

The short circuit current affected by the input-signals' slope, cell design, and the processing...