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This is what I came up with, I think it will work but would like some feedback from the community. Thanks for the help. The last two blue signals in the timing diagram are node D and out.
I have data coming at 2*clk and I want to clock the data into half the clock (clk) without losing data. For example, if I have 16 bits coming in at speed 2clk, I want to capture it in domain running at clk and perhaps ouput 32 bits of data in the clk domain, thus capturing two cycles of data...
Thanks for responding. I encountered the disk space error only after I have been plotting only the points I click on the schematic. I ran out of space doing it that way. I googled the .trn file being big, and someone said to do go to outputs, save all, and check the box that says only...
I am having a problem when simulating a circuit that my tran.tran.trn file is getting to be huge. The way I plot, is I go to output, to be plotted, select on schematic. I have a lot of inputs. I guess cadence is spitting out too much information into this file.
How can I reduce the size of...
I am using cadence virtuoso and spectre to simulate a complicated circuit I am building. I am trying to set up my stimulus properly so I wrote this .scs file. I am having trouble getting the piecewise linear function working. Can anyone please provide me with some help? I am very new to the...
Does any know of some good OVM tutorials? I am having trouble piecing together OVM an applying it to my design work. I have seen the OVM book but it is very heavy, dry and not beginner friendly.
Clock Dividing
Hi Everyone,
I have a highspeed clock coming out of a piece of ip that times data coming out on every edge of that fast clk. My design requires that I divide this clock by 2, and I am doing so by a simple flip flop configuration (no PLL is available to use). My concern is that...
Is it possible for say intel to take an off the shelf amd chip and be able to decode the architecture/technology within the chip? Perhaps they have equipment that could easily draw a schematic of fabricated chip. What do you guys think? I personally think that the cost to do something like...
Re: clock division
My other guess would be that in asics, you have the ability to add more sophisticated clock trees and so any skew in clock gating can be negligible.
Re: clock division
PLLs are fancy mixed signal designs. They allow you to divide down clocks cleanly. By cleanly I mean with minimal clock skew on the output clocks. Flip Flops do not have the extra circuitry to clean up the output. Therefore, when possible use plls.
Gating clocks adds skew.
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