Is it possible to do something like this?

[Digital-L0gik]

Is it possible for say intel to take an off the shelf amd chip and be able to decode the architecture/technology within the chip? Perhaps they have equipment that could easily draw a schematic of fabricated chip. What do you guys think? I personally think that the cost to do something like this is too great (not to mention the legal repercussions) without a specialized piece of equipment (which might be very expensive to begin with).

 

[radix]

Digital-L0gik,

Interesting question. I actually looked into this a little about 10 yrs ago. I don't think it's currently doable for any relevant size design.

First you would have to start by mapping out the metal layers. I'm not sure what the current state of the art is, but there are probably at least 10 layers of metal. You would have to strip each layer of metal off the chip to map the next layer until you finally get to the transistors themselves.

Then if you actually had some way of identifying all of the transistors and could create a netlist from all of the transistors and metal layers, what would you have? You would have a huge, flat netlist that would be pretty much meaningless.

The thing you would have to have then is some way to process the netlist to identify higher level functional blocks and create some kind of meaningful hierarchy. I think this step would be much harder than the flat netlist extraction.

Any out there have any insight into the state of logic extraction tools?

Radix

 

[ljxpjpjljx]

maybe we can discuss more about this topic, but it still a long way to go!

 

[pauloynski]

Ifyou have money enough this company will do the job https://www.semiresearch.com/

Added after 2 minutes:

They are from Lithuania

 

[Colbhaidh]

The equipment is not that expensive. It uses a CNC machine to mill off each layer by chemical mechanical polishing. As each interconnect layer is exposed, it is digitised by computer and hi-res camera. This can be later used to build a CAD database on a layer by layer basis.
At the transistor level, the source Drain regions have to be chemically stained to verify which are nmos and which are cmos. BiPolars are easy to spot as are LDMOS and power mos devices.
The physical sizes of the transistors can be digitally measured and a layout to schematic software does the rest.
It takes a very long time to do this and once you have a schematic, it does not necessarily mean you can fully understand the design.
Most chip companies by their competitors chips and reverse engineer them. They just don't admit it.
For 65nm and below, you might need an electron microscope to image each layer at the transistor level.

 

[Digital-L0gik]

Wow amazing. I am a cynic in some regards, so I believe companies do this regularly to weed out the competition hahaha.