Verilog Question - sequential order vs parallel

[woodde123]

Hi I have a verilog coding problem:

The following is what I want to do:

Once I press a button to load a number, the content of Value_1 is moved to Value_2, the content of Current_Value is moved to Value_1, and the content of input_data is move to Current_Value.
However, after executing the following code, Value_1 and Value_2 store the same value as Current_Value. How to fix the code? How can I get the statement executed in the specified sequential order?

Please help.

...
input [1:0] input_data;
reg [1:0] Value_2, Value_1, Current_Value, Current_Value_Temp;

always @ (posedge clk)

begin
if (reset) //active high
begin
Value_2 = 2'b0;
Value_1 = 2'b0;
Current_Value = 2'b0;
end

else if (load) //active high
begin
Value_2 = Value_1;
Value_1 = Current_Value;
Current_Value = input_data;
end

end
...

 

[jbeniston]

You should be using <= instead of =

 

[woodde123]

I tried "<=" but it gave me the same result.

 

[Digital-L0gik]

I believe non blocking assignments should fix this issue, I dont know why it didnt for you. How are you testing this code?

 

[tkbits]

By "pressing a button", I assume you are using real hardware.

Are you using the button to drive the clock signal?
If so, you need to debounce the clock signal.

If not, are you driving the clock signal with an oscillator signal, and driving the load signal with your button?
If so, then your clock signal is too fast. You aren't seeing the short moment when the outputs are different.