Clock Dividing - how to handle a late arriving edge?

[Digital-L0gik]

Clock Dividing

Hi Everyone,

I have a highspeed clock coming out of a piece of ip that times data coming out on every edge of that fast clk. My design requires that I divide this clock by 2, and I am doing so by a simple flip flop configuration (no PLL is available to use). My concern is that my divided clock edge might arrive later to flip flops that are grabbing some of the pieces of data riding out on the faster clk. The danger is in losing data. What can I do to handle the possibility of a late arriving edge?

Thanks.

 

[shelby]

Clock Dividing

First, the data being launched be the fast clock and captured by the slow clock can only be launched every other cycle, otherwise the slow clock will miss half the data. If your design takes care of that, then you have no worries. The two clocks can be grouped and balanced together during clock tree synthesis to ensure all clock edges arrive around the same time.

 

[Digital-L0gik]

Re: Clock Dividing

Yeah, i account for that. Thanks for the reply. You are right, clock tree synthesis will take care of it.