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memory dft collar
The mux is usually part of the BIST memory collar, or wrapper - whether this goes into the RTL code depends upon when you insert that logic - it could be done either at RTL or gates - are you doing a custom mBIST implementation? Or using a tool?
JMF
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Re: Regarding the Compression Techiques in Design for testab
The advertised strength is different between the two: the Mentor tool claims to be better at compressing many internal chains down to very few eternal chains, whereas the Synopsys tool claims to be better at catching small delay...
Re: latches in DFT
latches are very often part of a scan chain, but most commonly as "lock-up latches" that occur between clock domains, to guard against hold time violations in scan shift mode.
If you're curious and want more answers, go to DFT Forum - many DFT folks hang out there.
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I've never seen this in e-book form - and besides, it's pretty dated (old) - there are better books out now. Go check out the book list at DFT Digest.
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Re: Coverage Numbers
I assume that by "ATPG" coverage, you mean "stuck-at" fault coverage, and if so, the answer is fairly straight-forward: stuck-at coverage detects a more catastrophic fault, whereas the transition delay fault must be able to detect both a slow-to-rise or slow-to-fall - which...
There is a lot of material around - just google it - but if you have specific question... go ask at DFT Forum. We might be able to answer your question there...
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Re: AC and DC Scan
DC scan refers to stuck-at testing, AC scan is at-speed scan (for delay faults)...
John
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Re: skew scan enable
Route it like a clock. That's the simple answer. There are otther more complicated ways, used in logic BIST sometiimes, where the scan enable is pipelined, so that locally, there is less skew. But the general answer is that you have to use clock tree syntthesis on the...
I don't have my CTL book/spec with me, but try posting over at DFT Forum. There's people over there that probably use this more often...
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LOC is sequential, since it is essentially a double capture, and the ATPG tool needs to be able to store the state of the circuit after the last shift and first clock pulse of the capture in order to know what is expected after the second capture clock.
LOS is essentially the same as a simple...
What is it you mean by 'detach'? You want to unstitch the scan chains and redo them in another way? If so, I believe DFT Compiler will do that anyway, unless you specify them and put dont_touch on them. The tool is quite rude that way... ;-)
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Re: Scan chains
Absolutely, the number of scan chains is influenced by test time (which determines cost of test, and in turn the COGS ffor your device). The faster you can test a device, the cheaper it is to test, and the cheaper the cost of producing that part is.
Increasing the number of...
Re: Compression ratio
The economics of compression is just part of the story - what you can and can't do with compression is very design dependent, and tool dependent.
Less well-behaved designs cause unknowns to be propagated through the scan chains, which require masking them in the...
The MBIST result is not scanned out at-speed, so there is no worry there. If you're using JTAG to launch scan, the status signals are sent to the TAP controller asynchronously - no particular timing requirements. Then, normally, the results are scanned out at TCK speed.
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