DFT for core with BIST memory

[jaydip]

memory bist

I have a core which uses memory & that memory has BIST.

Question:
1) Will this memory be part of my scan chain ??

2) Do I require to bypass this memory when in scan mode (by inserting MUX in my verilog code)??

Can anyone elaborate more on this points please? or do you require more inputs ???

 

[ecijun]

bist memory

1 No
2 Yes, some eda tool can insert the MUX.

 

[enchanter]

memory scan collar

If we bypass that from the scan chain, how to do the BIST of those memories?

 

[wizard]

vhdl code for a memory bist

Scan test and Memory BIST are not carried out at the same time.

If we bypass that from the scan chain, how to do the BIST of those memories?

 

[jaydip]

memory bist rtl or gates

@ecijun
will eda tool add mux or it has to be done by designer explicitly in verilog code ??

 

[sunilbudumuru]

dft requirements bist

Hi Jaydip,

Points to note..

No need of inserting scan chain to your memory core.

You can bypass the memory at the RTL stage itself and make your design test friendly. (or)
You can bypass the memory by inserting the testpoints around it by using the eda tools.

Both MBIST and SCAN tests will not run simultaniously.

Beusure of the MBIST logic test ports are accessable to the test equipment. I mean, you need to control your MBIST core from outside and can observe the results.

You can plan the test architecture accordingly and so, u can either use different test potrs or can multiplex ur ports for testing of scan and MBIST.

Rest will be followed during the course of ur work.

Good Luck..
Hope this will help

For more info..
**broken link removed**

- sunil budumuru

 

[haneet]

dft topics 2009

to ,y knowledge the insertion of MUX is not done at the verilog level but is inserted at the physical level and as these dont' form the part of the logic but they are meant for testability.

plz correct me if am wrong....

 

[dft_guy]

memory dft collar

The mux is usually part of the BIST memory collar, or wrapper - whether this goes into the RTL code depends upon when you insert that logic - it could be done either at RTL or gates - are you doing a custom mBIST implementation? Or using a tool?

JMF
for DFT talk/info go to:
DFT Digest
DFT Forum

 

[enchanter]

bist memory test

In previous design, I think it is connected to the JTAG logic and use it to trigger the MBIST.

 

[sunilbudumuru]

memory wrapper dft

if it is so....its fine. But just double check the current design if it is same as before.

 

[stocking]

out of memory mbist

yes! It is simple!