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Route it like a clock. That's the simple answer. There are otther more complicated ways, used in logic BIST sometiimes, where the scan enable is pipelined, so that locally, there is less skew. But the general answer is that you have to use clock tree syntthesis on the scan enables.
If you want to know more, post over at DFT Forum - there are folks there that know about thi issue.
1. Develop CT (clock tree) on scan enable pin during PnR. This is because scan enable is a HFN.
2. During the test logic insertion itself you can avail the tool command option to balance the skew on this scan enable pin. I believe Synopsys DFT compiler has this option. Please verify.
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