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hi there,
could anyone explain me the difference between a logical and non-logical fet?
Is there a difference in dependance of the gate-source voltage?
kind of a newbie. Trying to simulate, but getting a model xx has not been defined error. No idea what i'm doing wrong. Simulations worked before, so probably i messed up something.
Anyone who can help me?
bode plot op amp
what you see are more poles at f=1e8 [Hz]. Each pole adds phase shift, but phase shift larger than minus 180 degrees is subtracted from plus 180 degrees (kinda fuzzy explanation). Basically what you are seeing is that the phase shift is clipping.
Also the magnitude shows a...
Hi guys, anyone has any idea how to measure a capacitance without letting the voltage over the capacitance becomes larger than 0V. Needs to know the parasitic capacitance on a port which can not become larger than 0V (design constraint).
Re: negetive voltage
how would you create such a current sink? Can i just use an NMOS with the source connected to a negative voltage, which is low enough to make sure that the NMOS does not go into triode if Vds becomes too low?
that totally depends on your application. If you want your amplifier to output a current you want a high output impedance. Same goes for your input impedance, if you want to amplify a current you don't want your input imp. to be high, but low.
i'm a little in darkness here guys, maybe someone can shed some light into it. Looking at the picture, am i generating a negative voltage with respect to ground here?
Re: why do transistors with same W/L have different performa
your width of transistor B is 4 times larger than transistor A. The gate-source capacitance is proportional to the width, therefore also 4 times larger. The decreases you unity gain bandwidth of your transistor with a factor 4. (not...
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