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When i give -debug_all option while compiling through vcs, I'm getting the following error. Can anyone please help me fix this
5NrIB_d.o:(.data+0xd0e8): undefined reference to `WrtMemCmp'
5NrIB_d.o:(.data+0xd130): undefined reference to `EnableRandomMemoryModePLI'
5NrIB_d.o:(.data+0xd170)...
If its a signal, hierarchical referencing helps, but for event it doesn't help... Or i dont know if there is a different way to refer to a event in the hierarchy..!!
I have a event emitted from a design file deep down in the DUT heirarchy, I want to capture this event in my testbench(TB). Is this possible in system verilog. If yes, then how ??
writing verification tests for fifos
yup...even i had a look at it....
but the thing is i din understand the perl script....was the perl script written by u???
fifo testcases
hi....i wanna verify my fifo.....
my testcases include
1] whether the data ovewrites if full.
2] no read on emty
3] writing the data n readin the data...to check if it is written correctly....
i wanna know if any othercases need to b checked.....
please if so let me know...
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