floorplanning and placement

[deepa122]

i' a newbie to floorplannin n placement....can anyone tell me what r sparecells n filler cells....

 

[vlsichipdesigner]

hi,

my 2 cents,

spare cells : Are extra functional logic cells like (nand, nor, flip flop, inverter, buffer,and, or...) all flavours of standard cells.
Why to have the spare-cells in the design, the name says spare then why to have in the chip and waste area is the question comes to your mind?
Obvious question, these cells are kept in a purpose in mind, these cells will be used, during ECO(Engineering change order), during later part in case if there is any requirement to change the die, then these cells will be used.

**broken link removed**

Filler cells: These may not have logic or functionality. Cells like decoupling caps, are used as filler cells,After layout (place and route), and before tapeout appling a filler cells is a step to ensure that there is no gap or empty area. so we fill the area with de-cap cells, or other cells so that the area would be covered or filled.

myprayers,

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[hiral.kotak]

Hi,

Actually the sparecells that you need to insert in your design will come from the top level designer. But if not then you can insert sparecells equal to 2% of your total design cells. And regarding to the
sparecell list, you can include the cells as per the max number of the types used in your design.
You should use, buffers and inverters, flipflops, muxes, and universal gates in a sufficient amount, so that any functionality can be formed with that and if any timing violations then you can use either buffers or inverters.
Endcaps are placed at the end of cellrows and handle end-of-row well tie-off requirements.
The library does not have well or substrate ties inside the cells. You are required to tie the NWELLS to Vdd and
the substrate to Vss before place-and-route using the FILLTIE cell.
It may help you.

Thanks..

HAK..