Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
No. 'Force' and 'release' are in VHDL2k8 standard.
Usage:
signal <= force illegal_state;
signal <= release;
You can do that also with ports but then you have to use 'force in/out'
Its simple ROM. You have to store "X" values in e.g. BRAM and read from it depending on "I" value. Lets say A = 1, K = 2 so considering your equation: x(i) = A + 2*i*K you will get:
x(0) = 1 + 2*0*2 = 1
x(1) = 1 + 2*1*2 = 5
x(2) = 1 + 2*2*2 = 9
etc.
So you fill ROM with values 1,5,9 etc and to...
Yes. Ive just tried to use simple 'process (all)' in ISE 12.3 but it didnt synthesize because of the error. However you can add new fixed_pkg or float_pkg packages to your designs and synthesize it. More you can read here:
**broken link removed**
Its a pretty nice tool. There are a lot of...
I suppose ISE doesn't support VHDL2k8. Definitely XST doesn't support it. So for it's only Riviera-PRO/Active and Synplify I think.
PowerPC looks nice considering floating point operations. However you do not specify how fast you want to calculate.
I cant tell you which board you should...
Automatisation?
Check webinar on Aldec, Inc - The Design Verification Company about Tcl. Or you can read about on Doulos - global independent leaders in design and verification know-how
Yes, its a part of FSM so in other state. Saying " It might be best to put a case statement on dataNumCnt to be explicit with you bit selection." you mean sth like this:
case dataNumCnt is
when 7 => buff <= 224vector (223 downto 192);
when 6 => buff <= 224vector (191 downto 160);
etc ?
Hi,
Ive got a module which send to me 224 bit vector. But i would like to divide this bus into 7 vectors 32 bit wide.
signal 224vector : std_logic_vector (223 downto 0);
signal buff : std_logic_vector (31 downto 0);
Now I would like to sample (7 times) in some sort of a loop like this...
Hi,
Is it (if is then how) possible to generate sine wave with frequency lets say 15kHz and 20kHz having only CLK of 48kHz ? Im asking because I wanted to generate this type of a signal and send it through I2S to the AC97 codec on my board and connect it to PC and see signal and its spectrum in...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
