OmarMokhtar
Newbie level 1
Hello Every Body ..
in Digital IC Design using Xilinx ISE Webpack , we've 4 types of simulations ..
1) Behavioral Simulation ..
2) Post Translate Simulation ..
3) Post Map Simulation ..
4) Post Route Simulation ..
I Know that the behavioral Simulation deals only with the HDL Code not with the synthesized circuit .. And I Know that the Post Map Simulation simulates with the Gates Delays .. And The Post Route Simulation Simulates with the Routing Delays and The Actual Circuit Delays inside the FPGA ..
Am I Right ????
But i'm bit confused about the Post Translate Simulation .. I Realize that its results are the same as the Behavioral Simulation (With out any kind of Delay) ..
What is the Post Translate Simulation Used For ?? What is the difference between it and the behavioral Simulation ??
Thanx Very Much ..
in Digital IC Design using Xilinx ISE Webpack , we've 4 types of simulations ..
1) Behavioral Simulation ..
2) Post Translate Simulation ..
3) Post Map Simulation ..
4) Post Route Simulation ..
I Know that the behavioral Simulation deals only with the HDL Code not with the synthesized circuit .. And I Know that the Post Map Simulation simulates with the Gates Delays .. And The Post Route Simulation Simulates with the Routing Delays and The Actual Circuit Delays inside the FPGA ..
Am I Right ????
But i'm bit confused about the Post Translate Simulation .. I Realize that its results are the same as the Behavioral Simulation (With out any kind of Delay) ..
What is the Post Translate Simulation Used For ?? What is the difference between it and the behavioral Simulation ??
Thanx Very Much ..