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The circuit is shown in the attachment,and the signal transformed is high speed signal,which means the TL impedance is 50 ohm for the switch edge of the signal,however it is 0 ohm for the high level of the signal. The output resistance is about 33 ohm,there is also a 75 ohm parallel terminated...
Since we don't want to add chip any more in our board, can I try approaches as below:
For the 3.3v lvttl to 2.5v lvttl ,can I use the divider resistor to attenuate the amplitude of 3.3V output to avoid damaging?
For the 2.5v lvttl to 3.3v lvttl ,can I place a pull-up resistor to 3.3V on the...
Recently in my project I need to design a JTAG chain which contains two diffenent voltage powered JTAG I/Os,one is 3.3V LVTTL,the other is 2.5V LVTTL.
The chain can be seen in the attachment,the JATG scanner itself is powered by 3.3V.So it surely can connect to the first chip in this...
Thank you for your reply.
But I think what you say is how to calculate the skew between several differential outputs of an certain interface,for example ,in the SFI-4 interface ,you can get the definite skew tolerance value between the clk and the data refering to the SFI-4 standard.
I...
Hi eveyone,
In my recent project,I try to lay a pair of differential output signal in the PCB.
the frequency of the signal is 5.6Ghz, my question is what the maxim of the skew should I control between the P line and N line in the PCB? How can I calculate the skew?
TKS
In the differential output circuit ,we usually use the AC couple.My question is in the PCB layout ,where should I place the capacitor? Should I place it near the output or near the input ?Dose these two pattern have some differences?
There is a driver in my circuit which is the LVPECL output, I use the AC couple between the output and the reciver.
It was konwn that output should connect 200 ohm resistor to the GND before the coupling capacitor to provide 14ma current for the OE output.
Since it's 1:10 driver,and each...
Well,the ASICs are different from FPGAs indeed.
I mean that the in the aspect of methodology,the FPGA design is similar with the ASIC design,
and I think it can be said that ASIC design is advanced FPGA design to a certain extent.
Leo
Thanks for your answer,but I am still confused about the jitter peaking.
what is the jitter peaking?
Does it come from the input jitter or from the PLL itself?
what is the relationship between the jitter peaking and the output jitter/input jitter?
Now I design a board which tansform one kind of frame (stm64) to another kind of frame (otu2).In this system the the clock of the output signal is tracking the input signal.So we add a PLL in the system to track the input clock.
The process is described as below:
First we recovery the clock from...
Re: What is DC to DC Converter
Hi thylacine1975,
Thank you for your reply.
I am also confuse about the definition about the output ripple and the output noise. It seems that output Ripple is caused by the change of the logic status of the chips which need this voltage to be supplied.While...
Hi Gavin,
You can download the protocol of the SFP form the internet.
I know this because I did the board design with the SFP before,you can refer this document which is a datasheet of oclaro SFP.
Re: What is DC to DC Converter
Hi thylacine1975,
I have a question about the performence differences between the linear regulator and the swith regulator:
It seems that there is less ripples and noises in the output of your DC/DC converter when you use the linear regulator instead of the swith...
some of these control signals can be controlled by I2C register inside the SFP or pin status outside of the SFP.
There is a standard of the register in the XFP.
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