What's the output jitter performance after several cascaded PLL?

[daraemon_liu]

Now I design a board which tansform one kind of frame (stm64) to another kind of frame (otu2).In this system the the clock of the output signal is tracking the input signal.So we add a PLL in the system to track the input clock.
The process is described as below:
First we recovery the clock from the input signal with the CDR,then we get f1,which is about 155.52Mhz.Secondly, we use a digital PLL to track it to generate f2,which is 167.33Mhz.Finaly we use the f2 to generate the new frame(otu2).
From this process,we can see the output clock is entirly from the input clock,so was the jitter.I know that the PLL can filter the low frequence noise itself,so the low frequence jitter of output maybe better than input.
Now I have a question:what wil happen of the final output jitter when we cascad several these board ?I mean we connect the first board output to the second board input, connect the second board output to the third board input......
like this:
stm64(input)=>otu2=>otu2=>stm64=>otu2......=>otu2=>stm64(final input)
Is there a limit of the number of the cascaded board? how can I calculate it?

 

[qieda]

Hi,

you wrote
>>> I know that the PLL can filter the low frequence noise itself,so the low frequence jitter of output maybe better than input.

I think a PLL will filter high frequent input noise. The low frequent input is tracked.

regarding your question.
I think if you cascade multiple identical PLLs you will run into issues. At least if your PLL have some noise peaking at the loop bandwidth (which is normally the case). Noise in the frequency range of the peaking frequency will increase with every board you add.

Here two paper, which you can find in the internet

**broken link removed**

**broken link removed**

 

[daraemon_liu]

Thanks for your answer,but I am still confused about the jitter peaking.
what is the jitter peaking?
Does it come from the input jitter or from the PLL itself?
what is the relationship between the jitter peaking and the output jitter/input jitter?

 

[chuckey]

Suppose the input clock has a uniform phase deviation of the carrier rather like FM. The phase lock loop will see this deviation and attempt to lock on to it. At low frequencies because its low pass filter will get rid of this cyclic component, it will lock onto the mean frequency. At very high frequencies the phase lock loop will not see this phase variation so it effectively looses lock. Now at some intermediate frequency, suppose the instantaneous input frequency rises, because of the time delay through the phase lock system, by the time it starts to reduce the frequency, the input frequency is reducing, so the total phase modulation is increased. For increased performance phase locked signal generators often have two phase lock loops with very different time constants to over come this effect.
Frank

 

[qieda]

Thanks for your answer,but I am still confused about the jitter peaking.
what is the jitter peaking?
Does it come from the input jitter or from the PLL itself?
what is the relationship between the jitter peaking and the output jitter/input jitter?

jitter peaking means that the ratio output jitter/input jitter is > 1.
The jitter transfer function (means the ratio output jitter/input jitter) is frequency dependent.

Normally
for low input jitter frequency (below the PLL bandwidth) the ratio output jitter/input jitter is 1 (it means the PLL will follow the jitter at the input).
for high input jitter frequency (above the PLL bandwidth) the ratio output jitter/input jitter is smaller than 1 (it means the PLL will filter the jitter at the input).

=> the PLL is a low pass filter for frequency jitter

between this two ranges (~at the PLL bandwidth) you can have a range which has a jitter peaking
(depending on the design of a PLL)
At this range the ratio output jitter/input jitter is greater than 1.
So the input jitter is amplified.

If you cascade multiple PLL which all have the same bandwidth your jitter may be amplified to such a big value that your system gets out of lock.

regards