daraemon_liu
Junior Member level 1
Now I design a board which tansform one kind of frame (stm64) to another kind of frame (otu2).In this system the the clock of the output signal is tracking the input signal.So we add a PLL in the system to track the input clock.
The process is described as below:
First we recovery the clock from the input signal with the CDR,then we get f1,which is about 155.52Mhz.Secondly, we use a digital PLL to track it to generate f2,which is 167.33Mhz.Finaly we use the f2 to generate the new frame(otu2).
From this process,we can see the output clock is entirly from the input clock,so was the jitter.I know that the PLL can filter the low frequence noise itself,so the low frequence jitter of output maybe better than input.
Now I have a question:what wil happen of the final output jitter when we cascad several these board ?I mean we connect the first board output to the second board input, connect the second board output to the third board input......
like this:
stm64(input)=>otu2=>otu2=>stm64=>otu2......=>otu2=>stm64(final input)
Is there a limit of the number of the cascaded board? how can I calculate it?
The process is described as below:
First we recovery the clock from the input signal with the CDR,then we get f1,which is about 155.52Mhz.Secondly, we use a digital PLL to track it to generate f2,which is 167.33Mhz.Finaly we use the f2 to generate the new frame(otu2).
From this process,we can see the output clock is entirly from the input clock,so was the jitter.I know that the PLL can filter the low frequence noise itself,so the low frequence jitter of output maybe better than input.
Now I have a question:what wil happen of the final output jitter when we cascad several these board ?I mean we connect the first board output to the second board input, connect the second board output to the third board input......
like this:
stm64(input)=>otu2=>otu2=>stm64=>otu2......=>otu2=>stm64(final input)
Is there a limit of the number of the cascaded board? how can I calculate it?