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HI,
i want to save in a ROM those vectors:
vector1(0 to 3)<=x"0000";
vector2(0 to 3)<=x"0001";
vector3(0 to 3)<=x"0010";
And each time i want to take one of them in order to xor it with another signal( MEP(0 to 3) ) which is coming from another component.
The problem is that during synthesis it...
is it possible to read from a file or somewhere else the message and save it as an input?I came across to a textio package while googling but i am not sure what is this for!
My problem is how to give as an input a variable length std_logic_vector.To be more specific i want to have a VHDL implementation that will take as an input an std_logic_vector(0 to variable) .How can i do that?
ok guys ! i solved my problem! Thanks again for your help! Finally the solution to my problem had to do with something else and not with the padding of the message! Anyway thanks for your help! Now my problem is how to give during the simulation as an input a variable length message! I am going...
man it is conventional if i write message2(511 downto 0 ) or messega2(0 to 511)...
Anyhow i write it i am gonna change the code so that in the simulation i see that message2 is "message1&1&0...0&128-bit binary representation of the length of the message1 in big endian form".
i know that with my code it is right , i can see it on the simulation! I am not sure if it is right according to the task which says : 128-bit binary representation of the length of the message1 in big endian form
So in the case :
message1(0 to 7)<="11001100";
l<=8(which is the length of the message1)
the outcome according to the previous would be:
message2(0 to 511)<="1100110010..0(383)0...01000";???????
"I guess, it's about changing the code to variable length message. But you have defined message1 with a fixed length of 8. So at best, you can make it work for a variable message length of 0 to 8. " --Yes this is one thing that i have in my mind to solve sometime, but not now.Now i really have...
message2 is a signal which i use for a xor gate with another std_logic_vector called hi.so i do after that:
message2 xor hi.So i don't have to make message2 as an output.I need it as a signal!
what i wanna do is exactly what the task above demonstrates! :P
You have a message M which is l bits.(So let's say that M(0 to 7)<="11001100" and thus len1(0 to 3)<="1000",len1 represents the length of the message in bits).Append the bit 1 to the end of the message M followed by 384-1-lmod512 of...
see the following for example.Here we have the message M<="011000010110001001100011" and the length of the message M is 24 bits.(here we have the out(0 to 1024) signal, something similar but it follows the same rule for the representation of the length of the message ).As you can see number 24...
the length of the message M(which is "11001100") is 8 bits, right?So the binary representation of the length of the message is "1000",isn't it?Integer 8 is "1000"(1000=8).So why should it be wrong that len1(0 to 3)<="1000" represents the integer number 8?No i do not have a vhdl library for the...
i don't have understood totally what you said ,however i hope that i can be more clear with the next.
len1(0 to 3)<="1000";
To be more specific in my case i have a task that says the following:
You have a message M which is len1 bits.(So let's say that M(0 to 7)<="11001100" and thus len1(0 to...
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