Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hello everyone,
I am working on a high linearity (~40dBm OIP3) X-band class A PA design. Output power should be in the range of 20~25dBm. The amplifier needs to be matched to 50ohm impedance.
Here is the problem. I used conjugate matching for the amplifier output (it can be treated as...
You can check out Jose Pedro's book "Intermodulation Distortion in Microwave and Wireless Circuits" and his publications. He describes how to predict IMDs using transfer function (Ic vs. Vbe in your case) in great detail.
Differentiating Ic vs. Vbe curve obtained from DC measurement may be...
Hi everyone,
I am using HFSS12 and Ansoft Designer 5 for EM co-simulation. I built some simple CPW structures in HFSS and incorporated them into Ansoft Desinger using dynamic link to HFSS. But the simulation results (S-parameters) given by HFSS and nexxim were significantly different (larger...
Re: How to decide Waveport size of a CPW and Batch mode in H
1. There is a tutorial on CPW port definition given by Ansoft. It is everywhere on the web. I would do comparison between simulation and measurement to determine the best configuration.
2. Create a parameterized design and do...
You can try delete previous database and do not add the last simulation result when updating your layout component. Or copy the problematic layout in momentum into a new design and re-create your component. It worked for me in the past.
Hi everyone,
I am going to purchase a Dell Precision workstation with dual Xeon quad core CPU for HFSS. But I am not sure which OS is better for HFSS, linux or windows? I have only used centOS linux in the past. Most of simulation softwares we are using are running on linux (IC design and...
wilkinson combiner design
I am working on a monolithic CPW 4-way (maybe 8-way in the future) 2watts Wilkinson combiner with center freq 20GHz. BW is 4 GHz. The substrate is GaAs. The size is the major concern in this case. I want to use single-stage design to reduce the size.
The problem is...
define strips
Hi, I am designing a CPW circuit on InP substrate. I need to deposit both gold and titanium strips on the surface. They are on the same layer. Then how can I define the substrate in ADS Momentum? I can not map more than one metalization layer between two insulation layers...
ads momentum simulation resistor
Hi, I am working on a CPW wilkinson combiner. I get confused about the port types to use. Should I use differential or internal? ( on strips ). And I want to use thin film resistor as the isolation resistor. Where should I simulation them, in the layout or...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
