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Recent content by clj023

  1. C

    Any good book on analog design

    I also recommended the book by Razavi . I read once and once and learned more and more
  2. C

    FIFO - Synthesis or Manual ?

    just divide two part Analog part: just as you say,do circuit gate level design. Digital part: use hdl language to implenment FIFO,then do function simulation,Synthesis. After layout ,do postsim as possible!
  3. C

    what is the difference of Registerfile and SRAM?

    I agree with the second reply. To same capacity ram: REG---high speed more area consume SRAM--- low speed less area consuem Added after 6 seconds: I agree with the second reply. To same capacity ram: REG---high speed more area consume SRAM--- low speed less area consume
  4. C

    How does this circuit works?

    dc to dc power supply converter&regulator
  5. C

    need help in folded cascode design

    Very good material,thank you very much!!!
  6. C

    analog design flow...

    I suggest you start with one analog design book, such as CMOS analog circuit design by PE.allen.
  7. C

    One question in diode simulation with Hspice

    Thanks,sunking How could I reduce the m value?? I means how to reduce the diode area in layout?
  8. C

    cadence vs tanner L-edit

    I use cadence in my company and use calibra to run drc and lvs. It's my habit.
  9. C

    One question in diode simulation with Hspice

    * Diode P+/Nwell Area 80*500um^2 parameters: .MODEL P+_NW D ( JS = 2E-19 JSW=7.68E-20 + RS = 4.89E5 N = 0.9904 BV = 12 + IBV = 1E-5 IK = 1E-4...
  10. C

    capacitor and resistor layout question

    better capacitor layout
  11. C

    Looking for info about designing a CMOS circulator

    CMOS circulator Could you descript it in detail?? I can not understand what you said circulator.
  12. C

    Help: how to print capacitance at a node in HSPICE?

    .option captab Indeed,my simulation result is also no responce when I add option cadtab. Maybe our Hspice version do not support it??
  13. C

    Loop bandwidth of PLL

    pll loop bandwidth equation i could not understand fully the description upstair. Could you give me some paper for reference,Thanks
  14. C

    What are the types of IO pads?

    basic esd and i/o design sanjay dabral i agree with anjali In addtion, the ESD layout of I/O pad is very important also which may be requied by custom.
  15. C

    Tool that generates layout from Spice netlist or Verilog code

    verilog to layout? SE could do it which included in cadence software.
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