Tool that generates layout from Spice netlist or Verilog code

[FLEXcertifydll]

verilog to layout?

To reference the basic digital IC design text, that's a standard begin just like "Hello world!"

But this Adder has many layout solutions, based on the different calculate speed.

 

[rebel]

Re: verilog to layout?

use bc as the select lines to a 4:1 mux to pass thru a or a' or 0.

 

[hung_wai_ming@hotmail.com]

Re: verilog to layout?

You need synthesis library to generate the RTL that u have
and use design compiler for commercial purpose.
For your simple case, just use schematic capture and draw it down
is good enough

 

[andy2000a]

Re: verilog to layout?

long time ago , siliconComplier can do it ..

many year ago, Cadence synergy can read verilog convert to GDS ..

I think , they need a unit tool can convert gate level ==> GDS ..
for design small cell use

by the way , have any tool can Spice --> GDS ?
like OPA circuit ==> GDS layout .


I use google find some tool called "PLL compiler" can synthesis
GDS PLL layout

 

[daf]

Re: verilog to layout?

lots of eda tools can do that, but not total conversion, you still have to do some editing. For custom tools, normally it can help you to generate the devices using pcell(if you are using cadence tools), then you have to do custom route or autorouter for routing.
for digital tools you needs a standard cells, then you have to auto route for routing.

 

[adscrz]

verilog to layout?

>you also can use cadence ic5 environment to do the same.

Which tools in IC5 do this job ?

 

[dreamscome]

verilog to layout?

magama tools can do it

 

[clj023]

verilog to layout?

SE could do it which included in cadence software.

 

[dr.farnsworth]

Re: verilog to layout?

Hi,

I have a very specific question related to the flow logic synthesis(Design compiler)-->layout generation(Encounter)..

how to transfer the design synthesized in design compiler to layout generation tool encounter.. what are the files required to do this ?

regards,
Dr.farnsworth