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Recent content by ckaa

  1. C

    memory mapped tristate slave

    I am assuming you are talking about an altera FPGA. If yes then this might help - www.altera.com/literature/manual/mnl_avalon_spec.pdf
  2. C

    writing output data from FPGA into a file in PC

    Another suggestion - If by chance you are using an Altera device, there is a UART ip core included and you could use the NIOS and some C code and implement the whole UART pretty easily, can skip the whole implementing the UART in HDL phase.
  3. C

    ProASIC3 and DDR2 -- STL 1.8v question

    How about using a LVDS to SSTL level translator - try Pericom or IDT.
  4. C

    Initialization of FIFO using ModelSim Testbench

    If I understood you right this is what you want to do - Bring out your FIFO signals as ports in your i2c core instantiation which will allow you to access your FIFO signals in the testbench. Now you can manipulate your FIFO signals in your testbench.
  5. C

    Help With Altera FPGA + PLL

    The top right corner of the Megawizard plug-in manager has a button called Documentation. You'll find a PLL user's manual here which will explain in detail all the ports of the PLL module. Your PLL will work if you don't use the 'areset' and 'locked' ports. The 'locked' is asserted when your PLL...
  6. C

    Help With Altera FPGA + PLL

    You just need to instantiate a PLL using MegaWizard. In Quartus under the "Tools" tab you'll find the MegaWizard PlugIn manager. Open that and it's a wizard that will guide you on creating your PLL (ALTPLL is located in the I/O folder under installed plug-ins in the megawizard plug-in manager)...
  7. C

    plz help me in this verilog code

    You cannot have this -" #100 $finish;" in an always block(read up on "always blocks" in verilog). Move that "$finish" out of the always block if you want the $finish statement. Also when you say word do you mean 4bytes? Right now your code outputs 8 bits at a time.
  8. C

    Explain me how would this be assigned

    Re: Plz explain this You have an intra-assignment delay for a blocking and non-blocking statement. You should be able to figure this one out after going through this pdf - www.sutherland-hdl.com/.../1996CUG-presentation_nonblocking_assigns.pdf
  9. C

    i2c to i2c switch in FPGA

    Thanks for the info, appreciate it!
  10. C

    i2c to i2c switch in FPGA

    Well I guess I have to define a register interface in the FPGA and do the mux select via i2c.
  11. C

    i2c to i2c switch in FPGA

    Hi, Anybody ever implemented an i2c switch in FPGA? I am trying to implement a 1 to 10 i2c switch in a FPGA (functionally similar to PCA9548A from TI). I know there are ICs out there which would serve the same functionality but need to implement it in a FPGA. Any hints or suggestions about...
  12. C

    FPGA Code for pulse counter

    See if this link helps:
  13. C

    Altera ByteBlasterII with Windows 7

    Yikes, that doesn't seem pleasant at all!! I am sorry I couldn't be of more help...I am trying to migrate to a Windows7 machine but still haven't tried anything. If I do come across a Byteblaster solution will let you know!
  14. C

    Altera ByteBlasterII with Windows 7

    Have you gone through these posts on the Altera Forum : https://www.alteraforum.com/forum/showthread.php?t=19233&highlight=windows+7 https://www.alteraforum.com/forum/showthread.php?t=3534&highlight=windows+7 From what I gather I think using drivers from Quartus 7.1 or 6.1 maybe a...
  15. C

    verlog code for 4 bit parallel adder

    you could use this as a starting point. There maybe minor errors in the framework below: module adder_tb(); reg clk, reset; reg [3:0] a,b; reg carry_in; wire carry_out; //adjust your delay according to your reset pulse width initial begin clk = 0; reset = 0; #20 reset = 1; #20 reset =...
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