ProASIC3 and DDR2 -- STL 1.8v question

[domno]

Hi everyone,

I'm trying to interface an Actel ProASIC3 FPGA with a DDR2 DRAM chip, at the lowest possible clock speed at 125MHz. I'm still new to hardware design and still have alot to learn, but I am always glad to learn more.

So, my problem is that the ProASIC3 FPGA only supports LVTTL/LVCMOS (1.5V/1.8V/2.5V/3.3V) and LVDS I/O logic interfaces.
I'm reading in the DDR2 datasheets that the single ended I/O used with DDR2 DRAM is SSTL 1.8V -- so I am now wondering if it still is possible to use LVTTL/LVCMOS 1.8V to interface with the DDR2 DRAM, maybe with the help of some passives?

I would really like to use an Actel FPGA so any advice here is welcome.

Thanks!

 

[ckaa]

How about using a LVDS to SSTL level translator - try Pericom or IDT.

 

[permute]

yes, this should be possible, as long as the lvcmos IO are fast enough. you can add the terminations extrernally. This probably won't be needed other than for EMI performance.