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Recent content by childs72

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    [SOLVED] Verilog print out %d longer than 32bit

    Good day, Anyone can share how to (in Verilog) print out signal >32bit using %d? Example I used: reg [49:0] my_var; initial $display("%d", my_var); The result I got is not my_var, thus i suspect %d is limited to 32bit. Is there any way I can print out my_var in decimal format? Thanks!
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    exclude certain clock from clock gating in DC_SHELL

    Hi, How may I exclude certain clock from clock gating in DC_SHELL? Thanks, Childs
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    Questions on DFT autofix

    Good day, I am currently trying to bring in DFT to the design. I am still in reading, not yet in implementation stage. However I have 2 questions on DFT autofix as below: 1. DFT DRC requires muxing on certain clock path & reset path. These muxing should be implemented at RTL or using DFT...
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    DFT & ATPG Tools enquiry

    Hi guys, I am doing assessment on which DFT & ATPG tools to go with. I hope to get some comments/opinions from the forum for questions below: 1. Which DFT (Scan Insertion Tool) is leading the market? 2. Which ATPG tool is leading the market? 3. What is your comments on DFT/ATPG tools you used...
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    PNR inserts more clock buffer than needed. What to do?

    Good day, I am designing a low-speed (2MHz), low-power system. During PNR , I observe that PNR inserted ~40 clock buffers for clock tree until my design is seeing ~60% power consumption due to these clock buffers. There is only ~150 registers in the design. Quick check on PrimeTime is telling...
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    Post-synthesis simulation problem due to RTL clock gating

    Thanks jbeniston. Agreed that I should look into the cell library for clock gating latch. Meanwhile, apart from using clock gating cell, is there anything improvement that can be done on my gating technique?
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    Post-synthesis simulation problem due to RTL clock gating

    Hi guys, I had implemented clock gating using RTL similar to below. It works well during RTL simulation. However, after synthesis, I perform simulation on post-syn netlist with sdf back-annotation. Simulation show the system does not function correctly. assign cg__clk = clk || !clk_gate_en...
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    number of bit of noise after division operation

    Hi, I am working on digital RTL design, however, I have to overcome this technical problem (which I believe it came under DSP subject) in order to hit the spec: 1. I have inputs from ADC (A & B), says, 10 bits data which consists 2 bits of random noise. I perform a division Z=(A*2^10)/B. In...
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    Can I clock gate my block after writing data into it for, says, forever?

    Thanks ads-ee! Took a quick look at flip-flop, so it seems like flip-flop output is merely "refreshed" but not "powered" by clock trigger. I suppose I got myself confused with the idea that DRAM requires periodically "recharge" its content (it's DRAM... right?) :bang:
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    Can I clock gate my block after writing data into it for, says, forever?

    Hi, I have some basic idea on how clock gate works & how it may reduce power consumption. Here is a scenario I am curious with: Says I have a design, and I have a bundle of configuration registers. For operation purpose, I just need to write my configuration registers for once when I power up...
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    power estimation & power table (when used in DC & PTPX)

    Hi, I had ran power estimation on DC & on PTPX (with .vcd file). I used same libraries for both tools. DC is able to report power without warning/error. However, PTPX complaint one of my IP does not have valid internal power table in its library... 1. After opened the .lib of the IP, I found...
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    power estimation with or without forward .saif

    Hi, it seems like we may perform power analysis with or without using forward .saif file. Can anyone explain what is the difference? Thanks. reference: pg 15-5 **broken link removed**
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    about x-prapagation of double flop during gate simulation

    Hi, While the current approach is estimated to work fine with my design (which is running at less than 100MHz), I am really interested to understand how to properly sync the data at high frequency. So far I only aware of double-flop technique to sync single bit data to safely avoid metastable...
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    about x-prapagation of double flop during gate simulation

    Thanks guys. Finally I am able to confirmed with my friend that what he saw before (where x-propagation is gone after double-flop implementation) is simulated with notifier turned OFF. So everything makes sense now :)
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    about x-prapagation of double flop during gate simulation

    Hi, we are seeing gate level simulation (with sdf annotation) that shows "x" after double-flop stage. I suggested that x-prapagation of double flop is not handled properly by the simulation. However my friend beg to differ as he claimed he seen gate level (with sdf annotation) simulation where...
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