childs72
Member level 1
Good day,
Anyone can share how to (in Verilog) print out signal >32bit using %d?
Example I used:
The result I got is not my_var, thus i suspect %d is limited to 32bit. Is there any way I can print out my_var in decimal format?
Thanks!
Anyone can share how to (in Verilog) print out signal >32bit using %d?
Example I used:
Code Verilog - [expand] 1 2 reg [49:0] my_var; initial $display("%d", my_var);
The result I got is not my_var, thus i suspect %d is limited to 32bit. Is there any way I can print out my_var in decimal format?
Thanks!