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Recent content by chandhramohan

  1. C

    handling glitch from Clock out of PLL going to Flop in SDF

    clock out pll out Hi, Im doing gate level timing simulation. Im getting in glitch in PLL clock out, which translates as X (during glitch period), when it passes through clock tree buffers, this clk with glitch goes to CLK Divider flop ( no timing chk is added to clk divider flops), but still...
  2. C

    sdf annotate question

    sdf annotate in vhdl Hi , For ncverilog if your sdf file has min/max/typ corners then use either +mindelay or +maxdelay switch in compile options to chk WC , BC . Or else u can specify in the testbench along with $sdfannotate(filename , top ,min/max) . Regards Chandhramohan
  3. C

    Looking for materials related to transition faults

    Re: Transition faults Hi, You can check for the document which i've posted in our site below . Regads Chandhramohan
  4. C

    AC-JTAG with Cadence or Synopsys products. Is it possible?

    ac jtag instructions Hi , Now I think Synopsys have come up with 1149.6 implementation .We have a design in which Synopsys tool was used to implement dot6 .Since it's new it had issues regarding dot6 compliance . Regards Chandhramohan
  5. C

    how to do flash bist?

    Hi dr_dft, Thanks for sharing the link ,it has got some intresting & usefull documents on DFT . Regards Chandhramohan
  6. C

    How to implement DFT with single scan clock

    Hi , Eventhough you convert all DFF -> SDFF of all chains ,if there are multiple clock domain flops in a chain ,then to handle this clock muxing is done .Also if the paritcular clock is not handled from the top level & its generated internally .Then test_clk has to be muxed with func clock...
  7. C

    how to implement DFT for DDR2

    dft for ddr2 Hi, Yo can do DFT for the DDR2 / HSS / SERDES . But some special care needs to be taken . As for as JTAG is concerned you need to consider the TX & RX lines as clock and add appropraite Boundary scan cell for those pins . Special pads needs to be added which can support that...
  8. C

    What's the purpose of DFT (design for test)?

    Re: DFT :design for test Hi , Before sending your chip/design to the end customer ,we need segregate the good working chip & the bad one before shipping. This can be done only by testing .So here functional testing will not be able to test all the nodes in the design .So for this we need...
  9. C

    AC-JTAG with Cadence or Synopsys products. Is it possible?

    ac-jtag Hi , I don't know about SYNOPSYS but CADENCE ENCOUNTER TEST arch doesn't support 1149.6 .I think no other tool have come up with dot6 implementaion as of now . May be LOGIC VISION you can try . Regards Chandhramohan
  10. C

    What is the difference between FSDB and VCD files?

    Re: Hi group... Hi , The VCD format of dumping is a standard format of signal value dumping which is accepted by all EDA simulation tools & EDA postprocessing tools .If you are running big simulations & need to dump the signals the file size of VCD will be large .Where as fsdb format of...
  11. C

    pls recommend books about ATPG

    Hi all, Below is a material which talks about trans fault testing , path delay & ATPG concepts & some of the practical design data obtained for the above modes of testing . I hope this will be usefull for all the DFT folks . Apart from this material , each ATPG tool will have its...
  12. C

    how to do flash bist?

    Hi, For FLASH memories also we can generate bist controller I feel . You get the memory testing spec sheet from the Vendor .There specifically you need to look for the sequence of alogorithm's required & also the algorithm of each one ,if thats not available in the mentor's algorithm list ...
  13. C

    funciton test pattern generation?

    Hi , Now a days all the ASIC's come with internal PLL .So the Source of the PLL will be considered based on the Maximum frequency of the Tester ( say 100 Mhz ) .From 100 Mhz using PLL multiplers / dividers we can arrive at the functional frequency .All these things will be decided at the...
  14. C

    funciton test pattern generation?

    Hi , After tapeout the chip will be tested for Functional patterns ( for the functionality of chip ) & Test patterns ( the ATPG test patterns which checks for defects in the chip by the DFT logic added in the design in Test mode) . All these are checked in the Tester level were the...
  15. C

    DFT strategy in semicustom flow

    Re: DFT strategy Hi , The exact dft logic insertion happens only at the netlist level . But the RTL can be coded DFT friendly which will reduce the effort after DFT insertion .There are some basic checks during scan inserion which can be handled well in RTL level itself .Like your reset...
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