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i guess it all depends on your interests...dont worry about salary as of now as a fresher....as in vlsi if u have exp. u have money.........sop go 4 it n explore more.............
ok....so there is a very gud book called hdl chip design by douglas smith.....this one has a chp. on latches and register.....gud one...ust read...it has given coding sytles for bith verilog and vhdl.....
latency means the time difference between your input arrival on input ports and that when output is received.......so this directly affects the max. freq at which your design will work.......
ram distributed
a distributed ram can be easily understood if u know a little bit about architecture of fpga......it consists of slices(reference to xilinx)......and each slice contains lut's and flops where bit values can be stored....so if ur code infers these storage elements as ram then it...
what does transistor level mean
rtl is register transfer logic.....basically it can be behavoral or data flow but should be synthesizable.......main stress will going for rtl level modeling is how data will flow between various stages of a design separated by registers(flops or latches).......
its a bit painful but very effective....wat u can do is that use the option of stepping from modelsim......that way u can check each n every statement being executed....and find bugs....also check for negative slacks in ur design and try breaknig the critical paths with flops inserted in...
i m definate that hyd. will emerge as the next fab city of not only india but 4 the world as a whole......as depicted from current scenario that major of the design cycle is being shifted to india and once fab starts there is no stopping to india's success......long live india and three cheers...
Re: Problem:Verilog Code
i think it is better to read the reference manual of the tool u want to use rather than lrm because every tool comes with different features and different synthesizable capabilities........so go through the manual of synplify to clarify ur doubts
low power design can be seen from many different prespectives,good architecture,proper routing,nicely prepared cell layouts in asic design flow,choice of mos family,fan-out considerations,types of external loads etc.....
scl chandigarh vedant
sandeepani is a gud one....i m doing a course in it rite now so i know that faculty is gr8 and u will also have no problem of licience n all......so go 4 it
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