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all guys: please discuss low power design

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xworld2008

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all guys: please discuss low power design
 

Hi,

There r variety of considerations that must b taken into account in low power design which include the style of logic, the technology used, and the logic implemented.
Factors that contributes to low power dissipation included spurious transition due to hazards & critical race conditions, leakage and direct path currents, pre charge transition, and power consuming transistor in used circuitry.
 

well dude.. what level of optimization are you lookin for.. architectural level.. algorithmic level or rtl level of power optimization..

u can use a varity of low power techs.. like clock gating, signal gating, low power busses, tryin to bridge CMOS floatin nodes, adiabatic computing or even DVS..

first describe ur design .. then go abt optimizing ur design to obey low power norms.

go thru some low power books.. by ananda chandarasekaran, gray yeap... if u go thru the books.. u wud understand the basics of low powerz..

search the forum..surely u wud get the books that ive mentioned above.

with regards,
 

low power design include:

1) use asynchronous logic design method.

2) use GALS(global synchronous local asynchronous)

3) use gated clock.

4) minimize signal activity, for example gray encoding.

5) use low power process, minimize distributed capacitance.

6) improve systen's architecture.

7) combine with software.





xworld2008 said:
all guys: please discuss low power design
 

Someone can tell the relevant articles materials or website of digital power management??

Thanks in advance
Best regards,jinsin
 

low power design can be seen from many different prespectives,good architecture,proper routing,nicely prepared cell layouts in asic design flow,choice of mos family,fan-out considerations,types of external loads etc.....
 

key word: Micropipeline, Sutherland, asynchrouns

asynchrouns circuit --> natural power management
 

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