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You're probably going to need to include a "reset" signal and use it to initialize your variables, like 'Z' and 'Tx' and make those signals registers which get setup in the clock process. Your compiler probably ingnores the initialization you are doing in the signal declaration.
S0_proc uses the constant Z, but that value isn't passed in. I don't see where you define the quatities "FPGA_FO" and "FPGA_SO" You should get an error when you use a value that isnt' defined. Same, I think, for "FU_FPGA".
A .INIT isn't the same as a reset value. Init happens at configuration time, reset happens whenever the GSR signal is asserted. You can initialize a ram array, but you can't reset it, at least in the manner described in the OP. Maybe there is a way to re-initailize the RAM from flash memory...
You can't infer a block RAM that way. Block RAM will only be inferred IF the code implements the BEHAVIOR of a block ram. Adding signals such as a reset will break this rule. Also, how do you propose to write an entire block RAM in a signle clock? That is quite impossible.
That's odd code: I'd try this:
when RcvData=>
if (BitCounter = PulseEndOfCount) then--173
Valid_out<='1';--indicates valid data
Code_out <=LineRD_in;--rx data is loaded in code_out->D in shift reg
end if;
if (DataCount ="0111") then
next_state<= StopBit;
else
--DataCount <= (OTHERS =>...
It means the simulator couldn't find the module the defines the component "rs232_rx" Either the software couldn't find the compiled module, or the interface to the module is incorrect ( see the discussion about "blackboxes" in your other thread ) or there was an error while compiling the...
When you instantiate a module in your code, you have an interface, which shows how the port signals connect to the module you're instanting the sub module into. Those port signals must match perfectly, all signals must be included, and all vectors must have the same indicies. Failure to do so...
Well, one thing I see is there is no way to ever get out of the state RcvData. Also, resetting should be done in the clocked process, and not in the combonatorial one. Try those changes, and if you stil get the mesage, I'll try to take a closer look.
Your simulation includes "blackboxes" which means the simulation software couldn't resove one of your modules. The software needs to be able to find your fifo's and the interface to them must be correct.
Those can be combanatorial statemets. It depends on if they are contained within a clocked process. It's entirely possibe to get a loop. Why not show us the code?
We are in the process of designing and deploying a number of embedded systems based on the Avalon switch fabric. Right in the middle of our efforts, out firmware engineer tell us that Linux won't work with the switch fabric that gets generated by the tools we are using. My question is why should...
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