Can an inferred Block RAM be updated with fixed data on RESET signal?

[joejoseph]

My Verilog code for a single port RAM( 256 * 8 ) has been synthesized as a block RAM.Verilog code is:
module single_port_ram_as_block_ram #(
parameter DATA=8,
parameter ADDR=8
)(
input a_clk,
input a_wr,
input [ADDR-1:0] a_addr,
input [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout
);

reg [DATA-1:0] mem [(2**ADDR)-1:0];
always @(posedge a_clk)
begin
a_dout <= mem[a_addr];
if(a_wr)
begin
a_dout <= a_din;
mem[a_addr] <= a_din;
end
end
endmodule


Now I need to have another input signal RESET to RAM.On every RESET input I need to linearly update block RAM contents in a SINGLE CLOCK.When i included RESET signal, RAM was not inferred as a block RAM.My codde is:
module ram_infer #(
parameter DATA=8,
parameter ADDR=8
)(
input rst,
input a_clk,
input a_wr,
input [ADDR-1:0] a_addr,
input [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout
);
reg [DATA-1:0] mem [(2**ADDR)-1:0];
always @(posedge a_clk,posedge rst)
begin
if(rst)
begin
mem[0]<=0;mem[1]<=1;mem[2]<=2;mem[3]<=3;mem[4]<=4;mem[5]<=5;mem[6]<=6;mem[7]<=7;mem[8]<=8;mem[9]<=9;mem[10]<=10;mem[11]<=11;mem[12]<=12;mem[13]<=13;mem[14]<=14;mem[15]<=15;mem[16]<=16;mem[17]<=17;mem[18]<=18;mem[19]<=19;mem[20]<=20;mem[21]<=21;mem[22]<=22;mem[23]<=23;mem[24]<=24;mem[25]<=25;mem[26]<=26;mem[27]<=27;mem[28]<=28;mem[29]<=29;mem[30]<=30;mem[31]<=31;mem[32]<=32;mem[33]<=33;mem[34]<=34;mem[35]<=35;mem[36]<=36;mem[37]<=37;mem[38]<=38;mem[39]<=39;mem[40]<=40;mem[41]<=41;mem[42]<=42;mem[43]<=43;mem[44]<=44;mem[45]<=45;mem[46]<=46;mem[47]<=47;mem[48]<=48;mem[49]<=49;mem[50]<=50;mem[51]<=51;mem[52]<=52;mem[53]<=53;mem[54]<=54;mem[55]<=55;mem[56]<=56;mem[57]<=57;mem[58]<=58;mem[59]<=59;mem[60]<=60;mem[61]<=61;mem[62]<=62;mem[63]<=63;mem[64]<=64;mem[65]<=65;mem[66]<=66;mem[67]<=67;mem[68]<=68;mem[69]<=69;mem[70]<=70;mem[71]<=71;mem[72]<=72;mem[73]<=73;mem[74]<=74;mem[75]<=75;mem[76]<=76;mem[77]<=77;mem[78]<=78;mem[79]<=79;mem[80]<=80;mem[81]<=81;mem[82]<=82;mem[83]<=83;mem[84]<=84;mem[85]<=85;mem[86]<=86;mem[87]<=87;mem[88]<=88;mem[89]<=89;mem[90]<=90;mem[91]<=91;mem[92]<=92;mem[93]<=93;mem[94]<=94;mem[95]<=95;mem[96]<=96;mem[97]<=97;mem[98]<=98;mem[99]<=99;mem[100]<=100;mem[101]<=101;mem[102]<=102;mem[103]<=103;mem[104]<=104;mem[105]<=105;mem[106]<=106;mem[107]<=107;mem[108]<=108;mem[109]<=109;mem[110]<=110;mem[111]<=111;mem[112]<=112;mem[113]<=113;mem[114]<=114;mem[115]<=115;mem[116]<=116;mem[117]<=117;mem[118]<=118;mem[119]<=119;mem[120]<=120;mem[121]<=121;mem[122]<=122;mem[123]<=123;mem[124]<=124;mem[125]<=125;mem[126]<=126;mem[127]<=127;
mem[128]<=128;mem[129]<=129;mem[130]<=130;mem[131]<=131;mem[132]<=132;mem[133]<=133;mem[134]<=134;mem[135]<=135;mem[136]<=136;mem[137]<=137;mem[138]<=138;mem[139]<=139;mem[140]<=140;mem[141]<=141;mem[142]<=142;mem[143]<=143;mem[144]<=144;mem[145]<=145;mem[146]<=146;mem[147]<=147;mem[148]<=148;mem[149]<=149;mem[150]<=150;mem[151]<=151;mem[152]<=152;mem[153]<=153;mem[154]<=154;mem[155]<=155;mem[156]<=156;mem[157]<=157;mem[158]<=158;mem[159]<=159;mem[160]<=160;mem[161]<=161;mem[162]<=162;mem[163]<=163;mem[164]<=164;mem[165]<=165;mem[166]<=166;mem[167]<=167;mem[168]<=168;mem[169]<=169;mem[170]<=170;mem[171]<=171;mem[172]<=172;mem[173]<=173;mem[174]<=174;mem[175]<=175;mem[176]<=176;mem[177]<=177;mem[178]<=178;mem[179]<=179;mem[180]<=180;mem[181]<=181;mem[182]<=182;mem[183]<=183;mem[184]<=184;mem[185]<=185;mem[186]<=186;mem[187]<=187;mem[188]<=188;mem[189]<=189;mem[190]<=190;mem[191]<=191;mem[192]<=192;mem[193]<=193;mem[194]<=194;mem[195]<=195;mem[196]<=196;mem[197]<=197;mem[198]<=198;mem[199]<=199;mem[200]<=200;mem[201]<=201;mem[202]<=202;mem[203]<=203;mem[204]<=204;mem[205]<=205;mem[206]<=206;mem[207]<=207;mem[208]<=208;mem[209]<=209;mem[210]<=210;mem[211]<=211;mem[212]<=212;mem[213]<=213;mem[214]<=214;mem[215]<=215;mem[216]<=216;mem[217]<=217;mem[218]<=218;mem[219]<=219;mem[220]<=220;mem[221]<=221;mem[222]<=222;mem[223]<=223;mem[224]<=224;mem[225]<=225;mem[226]<=226;mem[227]<=227;mem[228]<=228;mem[229]<=229;mem[230]<=230;mem[231]<=231;mem[232]<=232;mem[233]<=233;mem[234]<=234;mem[235]<=235;mem[236]<=236;mem[237]<=237;mem[238]<=238;mem[239]<=239;mem[240]<=240;mem[241]<=241;mem[242]<=242;mem[243]<=243;mem[244]<=244;mem[245]<=245;mem[246]<=246;mem[247]<=247;mem[248]<=248;mem[249]<=249;mem[250]<=250;mem[251]<=251;mem[252]<=252;mem[253]<=253;mem[254]<=254;mem[255]<=255;
end
else
begin
a_dout <= mem[a_addr];
if(a_wr)
begin
a_dout <= a_din;
mem[a_addr] <= a_din;
end
end
end
endmodule
How can the code be optimised to become a block RAM with RESET input?

 

[lostinxlation]

Is search function not working in your env ?

https://www.edaboard.com/threads/158673/

 

[qieda]

Hi,

in ASIC design a RAM does not have a reset value.
I do not know the behaviour in FPGA, but from your description it looks like the same behaviour.
So I think you have to use register for your design (as your synthesis tool does already)

regards

 

[Brownout]

You can't infer a block RAM that way. Block RAM will only be inferred IF the code implements the BEHAVIOR of a block ram. Adding signals such as a reset will break this rule. Also, how do you propose to write an entire block RAM in a signle clock? That is quite impossible.

 

[TrickyDicky]

Block rams cannot be reset. You have to manually set them location by location.

 

[permute]

FPGA's normally allow RAM to be initialized at startup. If reset is the chip GSR (Xilinx), then you can reset the ram. This only works if you use the global set/reset which will reset every part of the design.

 

[Brownout]

Rams cannot be reset, if you mean resetting the array data. As tricky dicky said, they must be cleared location by location.

 

[mrflibble]

To be clear, IF this is a xilinx BRAM we are talking about, then you can supply a reset value. But as permute already pointed out, this only works with the GSR (global set/reset).

From a user standpoint this means that in your verilog you can instantiate (as in, not infer) a block ram using one of the BRAM primitives, and then supply a .INIT parameter. During poweron the GSR will be asserted and the contents in the INIT parameter will then be loaded. Check the "Libraries Guide for
HDL Designs" for the part you are using.

Hope that helps.

 

[Brownout]

A .INIT isn't the same as a reset value. Init happens at configuration time, reset happens whenever the GSR signal is asserted. You can initialize a ram array, but you can't reset it, at least in the manner described in the OP. Maybe there is a way to re-initailize the RAM from flash memory, but you won't be able to code it in the ram HDL code. I think you need a flash controller and some special logic to write the array. It won't happen in a single clock cycle though.

 

[mrflibble]

A .INIT isn't the same as a reset value. Init happens at configuration time, reset happens whenever the GSR signal is asserted. You can initialize a ram array, but you can't reset it, at least in the manner described in the OP. Maybe there is a way to re-initailize the RAM from flash memory, but you won't be able to code it in the ram HDL code. I think you need a flash controller and some special logic to write the array. It won't happen in a single clock cycle though.

You are right of course. The reason to bring up the .INIT is maybe the OP asks for a reset, but could get away with initialization during configuration...

And just rechecked xapp463 ...

Global Set/Reset — GSR

The global set/reset signal, GSR, is asserted automatically and momentarily at the end of
device configuration. By instantiating the STARTUP primitive, the logic application can also
assert GSR to restore the initial Spartan-3 state at any time. The GSR signal initializes the
output latches to the INIT value. A GSR signal has no impact on internal memory contents.

Because GSR is a global signal and automatically connected throughout the device, the block RAM primitive does not have a GSR input pin.

 

[FvM]

Now I need to have another input signal RESET to RAM.On every RESET input I need to linearly update block RAM contents in a SINGLE CLOCK.

The words suggest clearly a separate reset input other than global reset. Initial reset won't care about a single clock cycle. So it's absolutely clear, that it can't work with internal RAM, neither for Xilinx nor other FPGA vendors. A logic cell implementation would involve 2048 registers plus a huge amount of multiplexers and decoding logic.

 

[joejoseph]

Thank you everyone for the reply.I think i have to code just as an array of registers and not a block ram.Also I have another question .Is "initial" blocks in verilog synthesizable.I have synthesized small programs with initial block.But what I have read is initial block is only for simulation purpose.

---------- Post added at 11:22 ---------- Previous post was at 11:20 ----------

does "for" loop take more number of resources than what i have written in the code??????

---------- Post added at 11:23 ---------- Previous post was at 11:22 ----------

does "for" take more resources than what i have written in my code????

 

[FvM]

FPGA snythesis tools are able to infer the power-up level of registers from an initial block. With some logic families, it may cause additional resource usage, if you are requesting an initial state opposite to other asynchronous set operations in the code. Usually, the tool will warn you about this.