Simulation and verification: WARNING:Xst:2036

[sns22]

HI;
I am using coregen to generate a fifo and use it to store data.data_out is assigned to the dout of the fifo.

I dont know why I am recieving this warning?
Is there any means to remove this warning.

WARNING:Xst:2036 - Inserting OBUF on port <Data_out<3>> driven by black box <fifo>. Possible simulation mismatch.

 

[Brownout]

Your simulation includes "blackboxes" which means the simulation software couldn't resove one of your modules. The software needs to be able to find your fifo's and the interface to them must be correct.

 

[sns22]

but i have stored the fifo.vhd in the same folder as other files and added it to the project also..created a top module where i have linked the fifo with the othr necessary ports in ther module..independently the fifo n top module are working clean..but when i combine the whole thing i m getting the warnings

 

[Brownout]

If you have any mismatch in the interface, the software will generate a blackbox.

 

[sns22]

mismatch in the interface?wht does this mean

 

[Brownout]

When you instantiate a module in your code, you have an interface, which shows how the port signals connect to the module you're instanting the sub module into. Those port signals must match perfectly, all signals must be included, and all vectors must have the same indicies. Failure to do so will result in the "blackboxes"