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Recent content by Blackuni

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    LDO Question about loop gain in relation to load current

    Hi Saro, Thanks, Its not in loop, I am validating it as individual CS stage since i am trying to evaluate the gain @ DC. I too aware that @ week inversion gain will be more and have used it for designing ultra low power opamp. but in this case i m not getting it.. Thanks,
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    LDO Question about loop gain in relation to load current

    Hi Saro & Erikl, Thanks, for now will consider DC gain @ Hz, LDO output voltage is 3v and feedback loop current is 5u so Rf1 + rf2 =600k = Req since we focus on DC output stage gain is gm3 x (rds || req) Here is the list of gm & Gds for different currents i got through SPICE simulation...
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    LDO Question about loop gain in relation to load current

    Hi can some one tell me how the loop gain increase with low/zero current with an LDO(refer to the attached screen shot) up to my understanding this should be other way. Say for example i have a three stage LDO structure with gain Aopen= A1 x A2 x A3(pass transistor) and my feedback factor...
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    spice explorer Error when import waveform

    Hi, This might be becoz of PSF version difference/support.. which spiceexplorer version is urs? Thanks,
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    A technical q. about HSpice output files

    Hi, its a waveform viewer from Synopsys and provided with Hspice. or u can try Cosmosscope too.
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    A technical q. about HSpice output files

    Hi, If u wnt more precession with your numbers printed, then better go with default binary format for tr# , ac#( this is the case when u set post=1) then use CustomWaveview to extract the data to table format with the precession u wnt.. When ascii format is used for dumping the waveform...
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    MOS device: intrinsic gain

    gm/Id vs Inversion coeff. (IC) wil give the info. But th aspect ratio need 2 b normalized so that comparison can be made.
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    [SOLVED] how to do a THD analysis for a diffirential amplifier

    Hope the document in below link helps..I would suggest to go thru it fully b4 https://www.edaboard.com/threads/67434/
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    [SOLVED] how to do a THD analysis for a diffirential amplifier

    I think there is command called "pdisto"
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    [SOLVED] how to do a THD analysis for a diffirential amplifier

    Hi, I presume that u wnt 2 simulate THD!! If so, Either u can try using distrortion analysis function in SPICE tools, In hspice its ".disto" , this will give better results only if there are no time varying signals. if you hve time varying signals thn do a transient simulation with appropriate...
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    Effect of W < L for a MOSFET in layout and later stages

    Active load
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    How to convert smart spice netlist to hspice netlist ??

    Hi, R u running the H spice simulation through some other tool ? direct run won't create this error!! if so, try running directly in H Spice
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    Effect of W < L for a MOSFET in layout and later stages

    Hi All, To add to my problem, I have binning based mos model, the max. L & W is around 20u and 100u. my calculations results in device with size w/l as 6u/300u, up to my understanding, the models will be accurate only in the binning rage, how to handle this?? Thanks,
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    Effect of W < L for a MOSFET in layout and later stages

    Thanks every 1, Here is the root, I tried 2 design a simple CS amp with 100nA current using 180nm process and land up in W<L Any pointer for very low (<100nA) design will be much helpfull. Thanks,
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    Effect of W < L for a MOSFET in layout and later stages

    Hi, Does any 1 came across any issues when using W < L for a mosfet, especially layout, fabrication related? Thanks,
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