LDO Question about loop gain in relation to load current

[Blackuni]

Hi

can some one tell me how the loop gain increase with low/zero current with an LDO(refer to the attached screen shot) up to my understanding this should be other way.

Say for example i have a three stage LDO structure with gain Aopen= A1 x A2 x A3(pass transistor)
and my feedback factor beta = Rf1/(rf1+rf2) so my loop gain will be Lgain = Aopen x beta

As per my expectation when current goes to zero/low my A3 will reduce. If A3 is reducing then total open loop gain as well as loop gain will reduce. but how its other wise?

thanks,

 

[saro_k_82]

Intrinsic gain of a stage is given by gm*ro. As current reduces for a fixed W/L, MOS enters weak-inversion where both gm and ro are at their maximum. So higher gain at low load currents is quite normal for LDO.

 

[erikl]

... but how its other wise?

Supplementary to saro's explanation above (which I agree is correct) the (in your case: non-dominant) output pole frequency fo=1/2π*ro*Co decreases, hence the gain drop changes from -20dB/decode to -40dB/decade. That's why the no-load gain curve crosses the load gain curve. A frequency decade later a zero seems to reverse the gain decline to -20dB/decade again.

 

[Blackuni]

Hi Saro & Erikl,

Thanks, for now will consider DC gain @ Hz,

LDO output voltage is 3v and feedback loop current is 5u so Rf1 + rf2 =600k = Req


since we focus on DC output stage gain is gm3 x (rds || req)


Here is the list of gm & Gds for different currents i got through SPICE simulation..
and I am not capturing the behaviour you have mentioned..am i missing somthing here?


*********
id 2.9745u (cutoff)
gm 912p
gds 1.7537p
*********

id 4.1455m (saturation)
gm 55.399m
gds 272.49u
**********

As its seen, the gain @ zero current is dominated by "req" and gain @ saturation is high
compared to gain @ cutoff..its 180nm foundry process.

Thanks,

 

[saro_k_82]

Blackuni, The numbers does seem to imply something odd, are you sure that the provided data keeps the loop in stable condition? The last stage seems to be providing a gain of -60dB which is definitely not right unless the transistor is in linear region. BTW did you notice that you mentioned 5uA bleed current, but it is showing up as 3uA

 

[Blackuni]

Hi Saro,

Thanks, Its not in loop, I am validating it as individual CS stage since i am trying to evaluate the gain @ DC. I too aware that @ week inversion gain will be more and have used it for designing ultra low power opamp. but in this case i m not getting it..

Thanks,

 

[varunkant2k]

Hi Blackuni,
This is normal behavior. I will explain in this way:
- Graph does not show phase response, without that we can't say the presence of poles/zeroes.
- As the final stage load current decreases, that means Req, at load increase: Req : Vout/I_laod.
- This increased Out put stage equivalent resistance implies to reduced pole. and thats why you see a sharp fall of gain plot.
- Full load response is single pole response ( another 2 poles and zeroes are not visible).
- No load response is showing two poles with reduced pole frequency shows system. System may not be stable.
- Instability comes with increased gain because of presence of multiple poles/zeroes at very low frequency.

 

[saro_k_82]

Even to evaluate the loop gain at dc, the loop has to be closed. Try using large inductors and capacitors to create unity feedback at dc and open for ac. From the operating point, find the gain of the last stage. I hope that would settle it.