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Recent content by bestvlsi

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    how to design a switch with discharge path for the stored charges

    Hi varunkant2k, Thanks for your reply. I get your first point that it affects the VCO , but can you please elaborate on the second point regarding the topology to achieve the same. What you said " Yes you can find it across VCO design." is not clear to me .... if you have any paper/research...
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    how to design a switch with discharge path for the stored charges

    LC VCO how to design a switch with discharge path for the stored charges Hi there, I am designing an LC VCO with switch capacitor bank in 0.18um process. This is being used in a radiation environment where it can face situation where there might be accumulation of charges in the capacitors...
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    Cadence UMC18 process which capacitor for RF frequency

    Hi All, I am making a VCO whose central frequency of oscillation is 2.5GHz . I ve been using MIMCAP_MM capacitors till now. But there are few RF capacitors also present in the UMC_18_CMOS library . Is there a need to go for those since my frequency of operation is high. Or will it do if I...
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    Cadence UMC18 process

    Hi All, I am designing a VCO block for PLL . I have few doubts 1. I am using 2 different types of MOS transistors a. Normal MOS transistors N_18_MM ,and b.RF MOS transistors N_L18W500_18_RF . Is is it ok to use two different types of MOS transistors in the design...
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    Cadence UMC18 process which MOS transistor for RF frequency

    Thanks jimito and erikl .. I am using the RF transistors now and indeed they are better as they are optimized for the number of fingers and the finger widths which are quite critical in RF applications. Since Ive seen in the layout that the finger width is kept minimal to reduce poly resistance...
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    Cadence UMC18 process which MOS transistor for RF frequency

    Hi All, I am making a VCO which should oscillate at a frequency of 2.5GHz . I ve been using N_18_MM and N_LV_18_MM till now. But there are few RF transistors also present in the UMC_18_CMOS library . Is there a need to go for those since my frequency of operation is high. Or will it do if I...
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    UMC 180 nm process capacitors

    Hi All, I am making a ckt in which i have to use a capacitor. Now the options i am having is NCAP_MM and PCAP_MM . Can anyone tell which one of these two has lower process variation. Regards.
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    Cadence layout problem in LVS

    Hi jimito13, Thanks for the reply :) . i had a discussion with my colleagues regarding the necessity of dummy transistors for active loads ... and they too agreed with my point of view that for the active current loads we need not go for the dummy devices... which are creating this problem ...
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    Cadence layout problem in LVS

    Hi All, I am doing layout for an NMOS differential pair with PMOS active load . The differential pair layout has passed the DRC and LVS. The PMOS active load has passed the DRC but is stuck with LVS. The problem I am facing in LVS is that its throwing up an error that the width of one of the...
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    Cadence differential pair layout

    Thanks a lot jimiti13 :)
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    Cadence layout simple question regarding current mirror and differential pair

    Hi All, Ive got 3 questions regarding layout of current mirror and differential amplifier:- Q-1. Ive got a current mirror with the pairs having large widths such that their finger numbers are 100 and 200 ( so as to keep the finger width <10 um )... now for this if i go for common centroid it...
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    Cadence differential pair layout

    Hi all , I ve to do layout for a differential pair with 2 fingers each. Now i read that for differential pair we should go for common centroid which means if the transistors are named A and B. Then AB BA is the desired layout. But i also read on the forums in some other posts that if the...
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    xilinx spartan 3E vs 3A starter kit

    Hi All, I am new to FPGA design and want to practise digital design . Can anyone give me pointers to which of the following two starter boards (spartan 3E vs 3A) should I go for since I wont be able to clearly tell whats the specifications mean related to digital design. Moreover are there...
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    vco design corner analysis CADENCE

    Hi all Brief Overview:- I am designing an LC VCO at 2.5GHz(cross coupled NMOS pair) in UMC 18 process with 5 bit binary weighted switched capacitor ckt for reducing KVCO. Pls note that this VCO is going to be a part of a PLL so i wont have the access to the control voltage of the varactor. I...
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    Regarding high third order harmonic in lc vco

    Cadence :- Regarding high third order harmonic in lc vco Hi all, Q-1 I am designing an LC VCO in UMC 18 process at 2.5 GHz. While doing PSS analysis I am getting third order harmonic at -43dB whereas the fundamental harmonic at -11dB. Ive read in some paper that the third order harmonic should...
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