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how many bits of decimal number u are getting? and from which kind of interface...? If you are getting decimal from software its better to convert it in software and take it on FPGA in hex form only....
hiii guys please reply as early as possible....
I am starting work with system verilog... Each and every material I got is messy.... please provide me some information for quick start to systemverilog.... is there any thing available on net....???
New to FPGA help me
In case of FPGA you need to be an good programmer only if you want to just programming the FPGA>>> As tools for simulation and synthesis of FPGA are to easy to catch up with....
Now as a programmer you must have to avoid some statements that are synthesizable for ASIC but...
yes if verilog 2001
no if verilog 95
how to define and use see the following link...
read line 15 in multi_array module...
https://www.asic-world.com/verilog/verilog2k2.html#Multi-Dimension_Array
as the above said...
initials are not synthesizable and how you will lose data due to reset... reset is made just once active and than it is not active it never effect data just put all memory element or say reg to some initial condition to set reg to some particular value that comes from input...
dear friend
when you define 8 bit adder you need to define carries of intermediate stages as wire ...
you cant put same ci as input to all 8 bit adder..
define wire c1,c2,c3,c4,c5,c6,c7 and replace module instance like this....
Added after 1 minutes:
add_1bit t0 ( r[0], c1, x[0], y[0], ci...
yes your code will work perfectly on rising edge of clock it will check for conditions of all three A, B and C statements in parallel
and it will create 3 reg for presentstate, delay and counter.
but as farhada suggested it is always better to use different process for all 3 and...
specially...
which ever signals are following critical path or for the signals you are facing trouble you can use timing constraint. i don't remember exactly how to use it but, you can assign delays like combinational logic should reach to reg input in particular amount of time... sort of constraints are...
serial to parallel conversion make 8-bit shift register at every 8th clock generate en signal that take 8 bits in 8 bit reg arry... where you will get 7 clock time to calculate for those 8 bits... hope you got
verilog codes using sin or cos.....pleeeeeeeeeeezzzzz urgent
forum is not an assignment supply service ...
it is made to share knowledge to whom you are interested in attempting...
first tell me how many clocks you are using... and if they are probably more than one... then sure due to them some issue is created... try to make design with single clock...
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