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Since the zero due to the ESR locates at 100KHz for exmaple, and the zero, as we known, is formed by the load capcacitor and the ESR, so we should only care about the ESR value at 100kHz.
LDO question
sometimes
Added after 1 minutes:
sometime the buffer may form another non-dominant pole in the gate of the buffer with first stage, if the loop gain is high enough and within the unity gain bandwidth
source follower for example.
sometimes merely buffer could not resolve the problem of stability, since the parasitic capacitance of the gate of the buffer forms anther non dominant pole with pre-stage, which may easily within unity bandwidth of LDO loop.
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