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Hi all,
In my design i have pll, cpu and embedded memories as black box. I am generating the stuckat reconfigure patterns using fastscan. I am loosing some 4.13% covergae because of black boxes only. This coverage loss is because of AU faults. I checked one AU fault, it is showing that the...
Re: ATPG Untesttable Faults
thanks for the reply sunil. yeah i have cpu, pll, ram and rom as black boxes. I am using the set_dft_configuration command for inserting the control as well as the observe points. But even then i am getting the same coverage. For atpg i m using fastscan. Do i need to...
Re: ATPG Untesttable Faults
Hi sunil,
Thanks for the reply. But that command will not work coz in default condition bidirectional ports are already fixed. I am putting the lines from synopsys manual:-
-fix_bidirectional enable | disable
Enables or disables the bidirectional disabling AutoFix...
stil2mgc
Hi all,
I have used design compiler and dft compiler for scan insertion for my design. when i checked my post dft drc report it showed me that there are no violations. I have converted the spf file to proc file for pastscan by using stil2mgc tool. I have generated stuckat patterns for...
timing violations
Hi,
can suggest me the kind of timing violations i can get in a design and how can i get rid of them? suggest some gud site or article from where i can get better idea. Your suggestions would be of great help for me. Thanking in advance.
Cheers
badola
Hi all
I am looking for a documnet which can give me some idea how to resolve the prescan drc errors. I am getting D1, D2, D3, D5 voilations. I ll be thankful to u guys if u can upload any material related to this. A tutorial will be of great help. Thanks in advance.
Regards and cheers
sudhanshu
Re: Compression ratio
The equations for Data Volume and Test Application Time Reduction
are calculated as follows:
Test Application Time Reduction = (Length of longest scan chain in
scan mode) / (Length of longest scan chain in
ScanCompression_mode)
Scan Test Data Volume
= 3 * Length of...
Re: Fault simulation
Performing fault simulation lets you determine the test coverage obtained by an externally generated test pattern. For fault simulation, you need functional test patterns that have been developed to test the design and have been previously simulated in a logic simulator to...
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