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Performing fault simulation lets you determine the test coverage obtained by an externally generated test pattern. For fault simulation, you need functional test patterns that have been developed to test the design and have been previously simulated in a logic simulator to verify correctness. The functional test patterns should contain the expected values unless you are using the Extended Value Change Dump (VCD) format. The expected values tell TetraMAX when and what to measure.
Fault simulation is also known as fault grading or functional grading.
Fault simulation checks whether the generated patterns have these features
1) accepatability to ATE
2)timing insensitive
3)recognizable format
Badola has given the correct answer from functional pattern point of view. If you want to know what it does during pattern generation then you have to understand the way the patterns are generated.
Pattern generation is a two step process,
1. Test Generator generates the pattern to detect a particular fault. During generation of pattern none of the constraints are kept in mind.
2. Fault simulator validates the pattern. During fault simulation if any of the constraints is violated then the pattern is dropped and a new pattern is created to detect the faults.
So, during ATPG as well, the fault simulator is running on creation of every pattern.
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