Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

ATPG Untesttable Faults - what to do to avoid them?

Status
Not open for further replies.

badola

Member level 5
Member level 5
Joined
Jan 4, 2008
Messages
89
Helped
7
Reputation
14
Reaction score
5
Trophy points
1,288
Location
bangalore
Activity points
1,786
stil2mgc

Hi all,

I have used design compiler and dft compiler for scan insertion for my design. when i checked my post dft drc report it showed me that there are no violations. I have converted the spf file to proc file for pastscan by using stil2mgc tool. I have generated stuckat patterns for the design. All patterns are passing. But i look into AU fault report i find au faults on functional pins which are not defined at the pad level wether those should be used as input or output as all of them are bidirectional in nature. I am bit confused why i am getting au faults on functional pins. Suggest me what should i do? Do i need to add control and observe point?
 

ATPG Untesttable Faults

Hello friend,

1. Whts the test coverage?
2.Have u fixed the bidi ports?

set_dft_configuration -fix_bidirectional enable
(or) manually u can fix the direction of the ports.

-Sunil Budumuru
asic-dft.com
 

Re: ATPG Untesttable Faults

Hi sunil,

Thanks for the reply. But that command will not work coz in default condition bidirectional ports are already fixed. I am putting the lines from synopsys manual:-

-fix_bidirectional enable | disable
Enables or disables the bidirectional disabling AutoFix utility. By default,
bidirectionals are autofixed.

i have a coverage of 96.07% for stuckat reconfigure mode. I am loosing some 3.63% coverage becuase of black boxes.
 

ATPG Untesttable Faults

Thts fine, but u just verify whether the tool has fixed or not.

In preview_dft -all report, u can see whether the bi-di got fixed by the tool or not. Just report the previw_dft .

By the way tool will not fix all the bi-di's by default. So, it is always better to verify the bi-di ports in post DFT netlist to see whether they got fixed or not.

By the way 96.07% coverage is good. if the BB's are kind of RAMs it is adviced to insert test points to improve the coverage.

-sunil budumuru
asic-dft.com
 

Re: ATPG Untesttable Faults

thanks for the reply sunil. yeah i have cpu, pll, ram and rom as black boxes. I am using the set_dft_configuration command for inserting the control as well as the observe points. But even then i am getting the same coverage. For atpg i m using fastscan. Do i need to use macrotest command for memories ? One more thing which i want to know what is the difference between atpg model for a memory than a simple memory model.
 

ATPG Untesttable Faults

1. which mode r u running dft compiler DB or XG?
2. How u r inserting the control (CP) & observe points (OP) using set_dft_configuration ?

Regarding atpg model for memories, i cannot give you the entire details here as it takes time. But, as u've BB'ed the RAMs, I can suggest the following.

Faults in the logic connected to data input, address and some control lines will be unobservable, while faults in the logic connected to data output will be
unobservable. So, just the CPs and OPs while inserting the DFT logic and proceed further.

This way u can get better coverage.

There are few other ways to handle memories in DFT, can see in asic-dft.com in couple of days.

Good Luck.

Sunil Budumuru
asic-dft.com
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top