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Hi VISWANADH,
In 65nm , 45nm and below technologies the worst delays are seen in "WCLCOM 0.81 -40 SS". This corner is also called as MAX_LT(LowTemp) corner. You can google for "Effect of Temperture Inversion in CMOS" and you will get know the reason for higher delays in this corner.
Ref...
Hi,
With large portion of common path between launch and capature, Can we have any (or huge) latency/Insertion delay? If not, then what are the consequences?
Regards
Hi,
When your doing block level PD and if you don't know/not provided IO delays then as friend_333 said you can apply IO delays as a % of your clock.
You can start with 20%-20% or 50%-50% it all depends upon other module location,their IO delay,net delay etc. w.r.to your module.
Regards,
Hi Randyest,
In antenna2.png, second diagram(Still antenna error) near the diffusion if i connect with lower layer(like how it is connected near the gate) still there will be any antenna error?
Re: filler cells
Hi,
>>But PnR tool can do the same optimization after inserting the filler cells.
If you insert filler cells before routing, cell placement is fixed and tool cannot move the cells for better placement optimization.
Regards,
Re: filler cells
Hi,
>>But why it is better to insert filler cells after routing?
Still P & R tool might be optimizing the design to meet the timing by moving the cell here and there, that is why filler cells will inserted after routing.
Regards,
Re: SOC Encounter
Hi nschiku,
Tool will create cell rows automatically at the time of loading the design( i.e along with Tech lef, Standard library lef, etc).
Once you are done with Add ring and Add stripes sroute will be used to route it and at the same time power rails will be created...
Re: zero wire load model
Hi Jitendra,
>>please tell me from where we get this zwlm and what are all the information it contains?
Wireload model is something which calculates the net delay based on the fanout of a particular gate. Basically its a statistical based model which gives the...
Yes, 1b will be the worst hold check.
Because at rise edge 7, launch flop launching the data and at the same time capture flop capturing the data (launched in the previous clk edge)and If there is very small (or no) delay between two flops or if there is clock skew between them then capturing...
The default setting is normal, that performs clock reconvergence pessimism removal with opposite-sense transitions in the shared path segment. When the two transition types produce different correction values, the smaller value is used. For same_transition, PrimeTime performs clock...
Hi Jitendravlsi,
In the Soc-Encounter installed path, in the doc section you will find foundation flow, which contains all the scripts which you have asked.
Regards,
Hi Sudheerprasad,
Leakage optimization is one of the low power implementation technique. And when you want use this technique during implementation process, your standard library should have both types of cells i.e High-vt and Low-vt.
>>a 3i /p nand gate,two nmos are having lower vt and third...
Hi Jitendra,
I have uploaded timing closure in soc encounter document. Go through "Data preparation section I guess which will answer your questions".
Let me know if you still have any doubts.
Regards
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