Hold checks on clocks with period 3 & 4

[prathima]

Hi,

I have a question on hold checks. Any help would be greatly appreciated!!

I have two clocks:

create_clock -period 4 -waveform {3 4} CLK1
create_clock -period 3 -waveform {1 2} CLK2

Setup checks :
1- launch edge at time = 3; capture time =4
2 -launch edge at time = 7; capture time = 10

and the worst case setup check is (1)

Hold:
For Setup(1) Hold checks would be:
1a -launch edge at time = -1 and capture edge at time = 4
2a- launch edge at time = 3 and capture edge at time = 1

For Setup(2) Hold checks would be:
1b- launch edge at time = 7 and capture edge at time =7
2b- launch edge at time = 3 and capture edge at time = 10

To me the worst case Hold check seems to be 2b, but synopsys document lists it as 1b.

Could someone please explain!!

Thanks & Regards,
Prathima.

 

[kujigaya]

For "Setup(2)" 1b and 2b, are they only for CLK2 paths?
What is the timing relationship between CLK1 and CLK2?

 

[arjun1110]

Yes, 1b will be the worst hold check.

Because at rise edge 7, launch flop launching the data and at the same time capture flop capturing the data (launched in the previous clk edge)and If there is very small (or no) delay between two flops or if there is clock skew between them then capturing flop will not capture the right data or there may be race condition. That is why 1b will be the worst hold check.

tclk-q+tcomb (or +tnet) < thold , will lead to a race condition

tclk-q - clock to q delay of ff1(launch flop)
tcomb - comb delay between the flops
tnet - interconnect delay between the flops

So in order to avoid race condition, tclk-q+tcomb(or +tnet) > thold