how to calculate INPUT and OUTPUT delay for a chip

[kotta]

Hi ASIC'ians

Could any body let me know "Is there any methodology exist to calculate Input and Output Delays of a chip".

Example:

Block A has an input DATA_IN and output DATA_OUT, how to calculate the input and output delays of block A.

Regards,
Sreedhar..

 

[lostinxlation]

I think timing analysis tool or synthesis tool (I forgot which one) usually have characterization feature, doesn't it ?

 

[rca]

input/output delay are the delay, you apply at chip level, if you plan to make a hierarchical synthesis, the tool will handle for you.

At chip level, you will provide the input/output delay based on your system constraints.

 

[friend_333]

hi

Normally input and output delays are some %age of your clock period.

Thanks

 

[rakko]

if you have access to primetime. load your netlist and sdf file and then issue a command like this to get the delay:

if the path is comninatorial:
report_timing -from chipa/in_a -to chipa/out_a

if its sequential, you have to do:

open primetime gui by typing primetime -gui&
highligt the path and select report timing from the menu.

 

[arjun1110]

Hi,

When your doing block level PD and if you don't know/not provided IO delays then as friend_333 said you can apply IO delays as a % of your clock.

You can start with 20%-20% or 50%-50% it all depends upon other module location,their IO delay,net delay etc. w.r.to your module.

Regards,

 

[kornukhin]

There are two cases: if your data synchronous or asynchronous with some external chip
(means have the same clock).

If data is async. input/output delays doesn't matters (can be zeroes).

If data synchronous you should calculate the time DATA takes to pass from source
trigger on one chip to another chip's I/O.
This time minus time clock takes to pass another chip's I/O will be the input_delay.

Same with output_delay.