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Recent content by anuradha.verma

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    Verification of power gating technique in VCS using UPF

    Hi, I want to use VCS for design with power gating .I have written UPF for the same. Can anyone tell me how can i do simulation using UPF.what are the steps and commands Thank you
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    how to change the type of file from unknown to program

    Hi, I have .db file which has type :unknown.i want to change the type :program Please tell me how i can do that
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    power report in design compiler

    Hi, I have synthesized my design using design complier. the power report looks like Cell Internal Power = -69.8378 pW (100%) Net Switching Power = 0.0000 uW (0%) --------- Total Dynamic Power = -69.8378 pW (100%) Cell Leakage Power = 795.0621 nW...
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    Traget libarary for synthesis of power gating

    Hi, I want to synthesis my VHDL code in design compiler.i want to use 90nm libaray.i have wriiten UPF for power gating implementation.. Can anyone tell me which library i should use for this purpose.i have SAEDPDK_EDK folder which contains many library .
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    Error while synthesizing design with UPF for power gating with design compiler

    Hi when i synthesize my design in design compiler following error appears "Error: The target_library does not contain an inverter characterized for operating condition (voltage = 1.080000V, process = 1.000000, temperature = 25.000000). (MV-006) This problem occurred at: <top design> Error...
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    writing UPF for power gating

    Hi, I am writing an UPF for power gating technique.I want to know what is the importance of power state table.whether its is optional or compulsory. and how i can write it. Thanks
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    error while verifying in formality

    i have used that .svf fle for set up.
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    error while using formality tool

    1) yes i used the svf file created by design compiler . 2) there are 20 signals in my design which are failing.
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    how to convert rc.local file back to tshell script

    hi, i did that.it got saved as t-shell script.but i needs to save as rc.local only...now what can i do for that.
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    error while verifying in formality

    hi, while verifying data in formality,verification of my design failed.I was comparing .vhd file with .ddc file(output of design compiler).the db while file used is saed90nm_typ.db. The debugging tool lists some of the signal name.Please tell me how can i remove those error.Do i need to change...
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    error while using formality tool

    HI Thanks ....i used the set hdlin_warn_on_mismatch_message "FMR_ELAB-X"...the error message changed to warning.and my file got loaded properly. but while veriying the design it got failed.the failed report lists some signals ....how to solve that.
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    Power compiler for power gating technique

    Hi thanks for the flow. i gone through the first 10 lines while tool is being invovked.it says power compiler is read with DC.
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    error while using formality tool

    hello, While loading the design(vhdl file) in formality tool following error appears "RTL interpretation message where produced during read. verification results may disagree with logic simulator" how can i remove this error
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    verification of layout of IC compiler

    Thanks ,we have herculus in our college computers.
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    verification of layout of IC compiler

    hello, i want whether the layout which i got is correct or not.Is herculus is the tool which should be used for this purpose.
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