error while verifying in formality

[anuradha.verma]

hi,

while verifying data in formality,verification of my design failed.I was comparing .vhd file with .ddc file(output of design compiler).the db while file used is saed90nm_typ.db.

The debugging tool lists some of the signal name.Please tell me how can i remove those error.Do i need to change my vhdl code.If yes where i can change .

thanks

 

[sam536]

Share the snap shot of log file. Problem is not defined properly.

 

[yx.yang]

If you use DC to synthesis the RTL design, DC will write out a file named "*.SV" (or maybe "*.SVF") to help formality to pass RTL Vs. Gate check.

 

[anuradha.verma]

If you use DC to synthesis the RTL design, DC will write out a file named "*.SV" (or maybe "*.SVF") to help formality to pass RTL Vs. Gate check.

i have used that .svf fle for set up.