Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

writing UPF for power gating

Status
Not open for further replies.
A

anuradha.verma

Junior Member level 3
Joined
Jul 12, 2011
Messages
27
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,449
Hi,


I am writing an UPF for power gating technique.I want to know what is the importance of power state table.whether its is optional or compulsory.
and how i can write it.

Thanks
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top